Abstract: Reagents A, B, C are added to an electrolyte bath for co-depositing tin-bismuth alloys (Sn—Bi). Reagent A is a larger acid molecule that binds to Bi3+ ions while reagent B is a small molecule that binds to the Bi3+ ions in spaces between the reagent A molecules. Reagents A and B reduce the standard electrode potential difference of Sn and Bi to permit co-deposition rates that yield a Sn—Bi alloy of 30-70% Bi by weight, around the 58% eutectic, with an alloy melting point below 180° C. for use as a low-temperature solder. Reagent C has a hydrophilic end that attaches to the electrode surface and a hydrophobic tail that is an aliphatic chain that attracts hydrogen gas, removing H2 gas from the electrode surface. Reagent C improves alloy microstructure by removing H2 gas generated at the cathode that can block Bi3+ ions from uniformly depositing on the surface.

Abstract: A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.

Abstract: A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.

Abstract: The presently claimed invention provides a method for optimizing an electrodeposition process of a plurality of vias in a wafer. Instead of simulating a large number of via on the wafer for via filling, a representative via is selected with the maximum value of critical factor, which is a function of process parameters. The filling of the representative via is simulated with different sampling points to find out the filling goodness in order to find out the optimized process windows of process parameters. An optimizer is also disclosed, which either provides sampling points or reduces sampling points under artificial neural network method. Calculation of filling goodness is used for evaluating via filling quality and further comparing among via fillings simulated at different sampling points. Consequently, the method of present invention is able to shorten the simulation time for via filling as well as provide a process window with high accuracy.

Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.

Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.

Abstract: The presently claimed invention provides a method for optimizing an electrodeposition process of a plurality of vias in a wafer. Instead of simulating a large number of via on the wafer for via filling, a representative via is selected with the maximum value of critical factor, which is a function of process parameters. The filling of the representative via is simulated with different sampling points to find out the filling goodness in order to find out the optimized process windows of process parameters. An optimizer is also disclosed, which either provides sampling points or reduces sampling points under artificial neural network method. Calculation of filling goodness is used for evaluating via filling quality and further comparing among via fillings simulated at different sampling points. Consequently, the method of present invention is able to shorten the simulation time for via filling as well as provide a process window with high accuracy.

Abstract: A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.

Abstract: Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in flash memory devices. In an example embodiment, a semiconductor chip may comprise a through-silicon via and a sidewall pad.

Abstract: A method of aligning electronic components comprising providing a positioning member 110 having at least one formation 120 for receiving an electronic component; said at least one formation having lateral boundaries 35, 36 for constraining movement of an electronic component; placing a first electronic component 10a in said at least one formation; and providing a force for actively aligning said first electronic component with a lateral boundary of said at least one formation. The force may, for example, be provided by tilting the positioning member, by providing suction or by using an actuator. An apparatus for aligning electronic components and a 3D system of stacked electronic components is also disclosed.

Abstract: A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.

Abstract: An electronic or micromechanical device having first (11) and second (12) surfaces and a via extending through the device from the first surface to the second surface. The via comprises integrally formed first (84, 86), second (82) and third (88) portions. The first portion (84, 86) extends from the first surface (11) to the second surface (12). The second portion (82) extends over a part of the first surface (11) of the device. The third portion (88) extends over a part of the second surface (12) of the device. Preferably the first portion comprises first and second parts, the second part extending through an active region of the device and having a narrower width than the first part. A method of forming and filling the via is also disclosed.

Abstract: High optical efficiency CMOS image sensors capable of sustaining pixel sizes less than 1.2 microns are provided. Due to high photodiode fill factors and efficient optical isolation, microlenses are unnecessary. Each sensor includes plural imaging pixels having a photodiode structure on a semiconductor substrate adjacent a light-incident upper surface of the image sensor. An optical isolation grid surrounds each photodiode structure and defines the pixel boundary. The optical isolation grid extends to a depth of at least the thickness of the photodiode structure and prevents incident light from penetrating through the incident pixel to an adjacent pixel. A positive diffusion plug vertically extends through a portion of the photodiode structure. A negative diffusion plug vertically extends into the semiconductor substrate for transferring charge generated in the photodiode to a charge collecting region within the semiconductor substrate.

Abstract: High optical efficiency CMOS image sensors capable of sustaining pixel sizes less than 1.2 microns are provided. Due to high photodiode fill factors and efficient optical isolation, microlenses are unnecessary. Each sensor includes plural imaging pixels having a photodiode structure on a semiconductor substrate adjacent a light-incident upper surface of the image sensor. An optical isolation grid surrounds each photodiode structure and defines the pixel boundary. The optical isolation grid extends to a depth of at least the thickness of the photodiode structure and prevents incident light from penetrating through the incident pixel to an adjacent pixel. A positive diffusion plug vertically extends through a portion of the photodiode structure. A negative diffusion plug vertically extends into the semiconductor substrate for transferring charge generated in the photodiode to a charge collecting region within the semiconductor substrate.

Abstract: One aspect of the present invention provides an electronic package, comprising at least a first module and a second module arranged on top of the first module, the modules together in the form of a module stack, wherein the first and second modules are adhesively connected together, each module includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over said die or dice, in each module the die or dice are bonded on said substrate layer via the metal layer, a plurality of channels formed generally vertically acting as vias to connect the metal layers and arranged adjacent to the die or dice in at least one of the modules, some or all the channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby the dice are electrically connected together, and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, commu

Abstract: There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component such that the holes are in alignment, and a pulse of laser energy is applied to form a bond between the metal plugs.

Abstract: An electronic or micromechanical device having first (11) and second (12) surfaces and a via extending through the device from the first surface to the second surface. The via comprises integrally formed first (84, 86), second (82) and third (88) portions. The first portion (84, 86) extends from the first surface (11) to the second surface (12). The second portion (82) extends over a part of the first surface (11) of the device. The third portion (88) extends over a part of the second surface (12) of the device. Preferably the first portion comprises first and second parts, the second part extending through an active region of the device and having a narrower width than the first part. A method of forming and filling the via is also disclosed.

Abstract: There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.

Abstract: A method of aligning electronic components comprising providing a positioning member 110 having at least one formation 120 for receiving an electronic component; said at least one formation having lateral boundaries 35, 36 for constraining movement of an electronic component; placing a first electronic component 10a in said at least one formation; and providing a force for actively aligning said first electronic component with a lateral boundary of said at least one formation. The force may, for example, be provided by tilting the positioning member, by providing suction or by using an actuator. An apparatus for aligning electronic components and a 3D system of stacked electronic components is also disclosed.

Abstract: An electronic device package comprises a substrate 110 having a first surface 110a and a second surface 110b opposite the first surface. An electronic device 120, 130 is positioned on the first surface 110a. An isolation layer 140 extends over at least a portion of the top surface of the electronic device. A redistribution layer 145 having one or more I/O lines extends over the isolation layer and the top surface of the electronic device. The RDL layer connects the electronic device to one or more first vias 160 which pass through the substrate 110 to the second surface 110b thereof. The electronic device may be an image sensor. A microlens 220 and protective parylene layer 230 may be fabricated over the image sensor. A method of manufacturing the electronic device package is also disclosed.