Abstract: The technology of this application relates to a package substrate that includes a substrate body. Each unit region includes at least one solder ball group. The solder ball group includes a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings. The first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball. The fifth solder ball is provided on a side of the parallelogram and is located between the first solder ball and the third solder ball. The sixth solder ball is provided on another side of the parallelogram and is located between the second solder ball and the fourth solder ball.

Abstract: A printed circuit board includes a connector insertion area including many rows of crimping holes, each row of crimping holes includes at least two pairs of signal crimping holes (SCHs), and each pair of SCHs includes two SCHs. In a row arrangement direction of the crimping holes, at least one ground crimping hole (GCH) is arranged on either side of each pair of SCHs. A depth of the GCH is greater than or equal to a depth of the SCH, the GCH includes a main hole and a shielding component on at least one side of the main hole, a part of a side wall of the main hole is a part of a side wall of the shielding component, and a sum of lengths of the main hole and the shielding component in a first direction is greater than a length of the SCHs in the first direction.

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: A semiconductor structure includes: at least one first conducting layer between a first wire and a second wire; a plurality of capacitor banks respectively located on the first wire, the second wire, or the first conducting layer, and two capacitor banks are located on each first conducting layer; a third wire is located above and connected to the first wire through a via hole, and a fourth wire is located above and connected to the second wire through a via hole; at least one capacitor plate located on the upper electrode layer, and upper electrode layers of two adjacent capacitor banks are electrically connected to a same capacitor plate; at least one second conducting layer located between the third wire and the fourth wire, and an orthographic projection of the second conducting layer on a plane on which the capacitor plates are located is located between two adjacent capacitor plates.

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: A printed circuit board includes a plurality of layer structures disposed in a stacked manner, and the printed circuit board has a disposing face. A differential pair unit and a shielding structure for shielding the differential pair unit are disposed on the disposing face. The differential pair unit includes two signal via holes, each signal via hole passes through the plurality of layer structures, and an anti-pad corresponding to each signal via hole is disposed on a ground layer through which the signal via hole passes. A part of metal of a ground layer is spaced between two anti-pads. Each signal corresponds to one anti-pad, and a ground layer is spaced between anti-pads.

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: A printed circuit board includes a connector insertion area including many rows of crimping holes, each row of crimping holes includes at least two pairs of signal crimping holes (SCHs), and each pair of SCHs includes two SCHs. In a row arrangement direction of the crimping holes, at least one ground crimping hole (GCH) is arranged on either side of each pair of SCHs. A depth of the GCH is greater than or equal to a depth of the SCH, the GCH includes a main hole and a shielding component on at least one side of the main hole, a part of a side wall of the main hole is a part of a side wall of the shielding component, and a sum of lengths of the main hole and the shielding component in a first direction is greater than a length of the SCHs in the first direction.

Abstract: The disclosure relates to a low toxic tripterygium neoglycosides, which is obtained by chemically processing tripterygium glycosides and adding triptriolide. The disclosure also discloses the application of the low toxic tripterygium neoglycosides. The tripterygium neoglycosides can effectively relieve renal pathological injury and urinary protein of nephrotic syndrome, attenuate the inflammatory level of the body, have obvious treatment effect on nephrotic syndrome, and have low toxicity and persistent effect.

Abstract: A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: The disclosure relates to a low toxic tripterygium neoglycosides, which is obtained by chemically processing tripterygium glycosides and adding triptriolide. The disclosure also discloses the application of the low toxic tripterygium neoglycosides. The tripterygium neoglycosides can effectively relieve renal pathological injury and urinary protein of nephrotic syndrome, attenuate the inflammatory level of the body, have obvious treatment effect on nephrotic syndrome, and have low toxicity and persistent effect.

Abstract: A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

Abstract: The invention relates to a preparation method of new-type nanoparticles for loading emodin, which comprises: using L.A, mPEG and stannous iso caprylate to synthesize a first intermediate product; using the first intermediate product, butanedioic anhydride and 4-dimethylaminopyridine to synthesize a second intermediate product; using the second intermediate product, 1-ethyl-(3-dimethylamino propyl) carbodiimide hydrochloride, N-hydroxysuccinimide and chitosan to synthesize a third intermediate product; using the third intermediate product and sodium periodate to synthesize a fourth intermediate product; using the fourth intermediate product and 5-amino-2-mercapto benzimidazole to synthesize the new-type thiolated nanoparticles. The nanoparticles loaded with emodin are used for intestinal tract dose, which may enhance the nanoparticles' adhesion ability, prolong residence time of drugs on mucosal membranes, and facilitate sustained-release of drug molecules.

Abstract: The invention relates to a preparation method of new-type nanoparticles for loading emodin, which comprises: using L.A, mPEG and stannous iso caprylate to synthesize a first intermediate product; using the first intermediate product, butanedioic anhydride and 4-dimethylaminopyridine to synthesize a second intermediate product; using the second intermediate product, 1-ethyl-(3-dimethylamino propyl) carbodiimide hydrochloride, N-hydroxysuccinimide and chitosan to synthesize a third intermediate product; using the third intermediate product and sodium periodate to synthesize a fourth intermediate product; using the fourth intermediate product and 5-amino-2-mercapto benzimidazole to synthesize the new-type thiolated nanoparticles. The nanoparticles loaded with emodin are used for intestinal tract dose, which may enhance the nanoparticles' adhesion ability, prolong residence time of drugs on mucosal membranes, and facilitate sustained-release of drug molecules.