Patents by Inventor Xuyen N. Phung

Xuyen N. Phung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7207014
    Abstract: In a computer system having a device and a communications link for communicating with the device. A method for dynamically managing power consumption by the computer system comprises associating a particular device identifier with the device. Communications are monitored over the communications link to determine whether the communications include the particular device identifier. A clock input is withheld from the device when the communications do not include the particular device identifier. Clock input is provided to the device only when the communications include the particular device identifier. The clock input causes the device to transition from a non-operational power conservative state to an operational state wherein the device consumes more power than in the non-operational state. A performance requirement is established for a task to be executed. Clock frequency is dynamically controlled according to the performance requirement established for the task being executed.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: April 17, 2007
    Assignee: St. Clair Intellectual Property Consultants, Inc.
    Inventors: Francisco Velasco, Xuyen N. Phung, Phillip M. Mitchell, Henry T. Fung
  • Patent number: 6813674
    Abstract: A dual-edge FIFO interface having a host FIFO interface operative to receive data from a host module on a single edge of a host clock, and determine situations when valid read data is present in a read data FIFO or when the read data FIFO is full, a target FIFO interface operative to receive read data from a target core module, transfer data out, and determine when the read data FIFO is full, and a register block in communication with the host FIFO and the target FIFO, wherein the dual-edge FIFO interface is operative to interconnect internal modules at a core logic level, a block level, or a chip level.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: November 2, 2004
    Assignee: St. Clair Intellectual Property Consultants, Inc.
    Inventors: Francisco Velasco, Xuyen N. Phung, Phillip M. Mitchell, Henry T. Fung
  • Patent number: 6115823
    Abstract: In a computer system having a device and a communications link for communicating with the device. A method for dynamically managing power consumption by the computer system comprises associating a particular device identifier with the device. Communications are monitored over the communications link to determine whether the communications include the particular device identifier. A clock input is withheld from the device when the communications do not include the particular device identifier. Clock input is provided to the device only when the communications include the particular device identifier. The clock input causes the device to transition from a non-operational power conservative state to an operational state wherein the device consumes more power than in the non-operational state. A performance requirement is established for a task to be executed. Clock frequency is dynamically controlled according to the performance requirement established for the task being executed.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: September 5, 2000
    Assignee: Amphus, Inc.
    Inventors: Francisco Velasco, Xuyen N. Phung, Phillip M. Mitchell, Henry T. Fung
  • Patent number: 5987614
    Abstract: Structure and method are provided for reducing power consumption in a computer system without sacrificing computer performance or inhibiting a computer user's rapid access to the computer. An identifier, such as a device address, network address, serial number, and the like, is associated with each device or resource. Communications over a communications link such as a parallel bus, serial bus, or wireless link, are monitored by each device to determine device identifiers communicated over the link, and these identifiers are compared to the identifier associated with the monitoring device. Each device monitors the communications and is responsible for self-controlling its operating condition to minimize power consumption. Each device includes a first component which operates continuously to provide the monitoring function, and a second component that operates in a low power consumption mode unless the first component signals the second component that its operation is needed during that time period.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: November 16, 1999
    Assignee: Vadem
    Inventors: Phillip Merle Mitchell, Francisco Velasco, Xuyen N. Phung