Patents by Inventor Xuyi Yang
Xuyi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395438Abstract: A semiconductor device includes a die stack having dies selected into the stack based on their thicknesses. After the dies are formed on a wafer and thinned, a metrology tool is used to determine the thicknesses of the dies in the wafer. These thicknesses are stored in a known thickness die (KTD) map, along with other information such as their standard and average deviations and their classification into a binning class. In one example, dies which have been classified into bin 1 (having an optimal thickness) are selected to provide a high capacity highly reliable semiconductor device. In a further example, dies of different bins are mixed and matched to provide a uniform, highly controlled overall die stack height.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Nagesh Vodrahalli, Chih Yang Li, Xuyi Yang, Cong Zhang
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Patent number: 11456279Abstract: A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.Type: GrantFiled: May 29, 2020Date of Patent: September 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Qi Deng
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Patent number: 11425817Abstract: A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.Type: GrantFiled: November 30, 2020Date of Patent: August 23, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Shineng Ma, Xuyi Yang, Chih-Chin Liao, Chin-Tien Chiu, Jinxiang Huang
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Patent number: 11302673Abstract: A semiconductor device is disclosed including one or more stacks of semiconductor dies vertically molded together in an encapsulated block. The semiconductor dies may comprise memory dies, or memory dies and a controller die.Type: GrantFiled: March 13, 2020Date of Patent: April 12, 2022Assignee: Western Digital Technologies, Inc.Inventors: Xuyi Yang, Cong Zhang, Chin-Tien Chiu
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Patent number: 11276669Abstract: A semiconductor device is disclosed including wafers of stacked integrated memory modules. A semiconductor device of the present technology may include multiple memory array semiconductor wafers, and a CMOS controller wafer, which together, operate as a single, integrated flash memory semiconductor device. In embodiments, the CMOS controller wafer may include semiconductor dies comprising ASIC logic circuits integrated together with memory array logic circuits.Type: GrantFiled: March 13, 2020Date of Patent: March 15, 2022Assignee: Western Digital Technologies, Inc.Inventors: Xuyi Yang, Shineng Ma, Cong Zhang, Chin-Tien Chiu
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Patent number: 11257785Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.Type: GrantFiled: March 13, 2020Date of Patent: February 22, 2022Assignee: Western Digital Technologies, Inc.Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Yazhou Zhang
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Publication number: 20220052002Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Applicant: Western Digital Technologies, Inc.Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
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Publication number: 20210400811Abstract: A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.Type: ApplicationFiled: November 30, 2020Publication date: December 23, 2021Applicant: Western Digital Technologies, Inc.Inventors: SHINENG MA, XUYI YANG, CHIH-CHIN LIAO, CHIN-TIEN CHIU, JINXIANG HUANG
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Patent number: 11189582Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.Type: GrantFiled: December 6, 2019Date of Patent: November 30, 2021Assignee: Western Digital Technologies Inc.Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
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Patent number: 11139277Abstract: A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.Type: GrantFiled: March 10, 2020Date of Patent: October 5, 2021Assignee: Western Digital Technologies, Inc.Inventors: Chien Te Chen, Cong Zhang, Hsiang Ju Huang, Xuyi Yang, Yu Ying Tan, Han-Shiao Chen
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Publication number: 20210151399Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.Type: ApplicationFiled: December 6, 2019Publication date: May 20, 2021Applicant: Western Digital Technologies, Inc.Inventors: Xuyi Yang, Fuqiang Xiao, Cong Zhang, Kuo-Chien Wang, Chin-Tien Chiu
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Publication number: 20210043602Abstract: A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.Type: ApplicationFiled: May 29, 2020Publication date: February 11, 2021Applicant: Western Digital Technologies, Inc.Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Qi Deng
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Publication number: 20200411481Abstract: A semiconductor device is disclosed including one or more stacks of semiconductor dies vertically molded together in an encapsulated block. The semiconductor dies may comprise memory dies, or memory dies and a controller die.Type: ApplicationFiled: March 13, 2020Publication date: December 31, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Xuyi Yang, Cong Zhang, Chin-Tien Chiu
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Publication number: 20200411480Abstract: A semiconductor device is disclosed including wafers of stacked integrated memory modules. A semiconductor device of the present technology may include multiple memory array semiconductor wafers, and a CMOS controller wafer, which together, operate as a single, integrated flash memory semiconductor device. In embodiments, the CMOS controller wafer may include semiconductor dies comprising ASIC logic circuits integrated together with memory array logic circuits.Type: ApplicationFiled: March 13, 2020Publication date: December 31, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Xuyi Yang, Shineng Ma, Cong Zhang, Chin-Tien Chiu
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Publication number: 20200411478Abstract: A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.Type: ApplicationFiled: March 10, 2020Publication date: December 31, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Chien Te Chen, Cong Zhang, Hsiang Ju Huang, Xuyi Yang, Yu Ying Tan, Han-Shiao Chen
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Publication number: 20200365554Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.Type: ApplicationFiled: March 13, 2020Publication date: November 19, 2020Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Cong Zhang, Chin-Tien Chiu, Xuyi Yang, Yazhou Zhang