Abstract: This invention demonstrates a technique to determine potentially redundant test patterns for a complex integrated circuit device. The technique utilizes test data from a large sample of product, thus including the effects of the process line and the actual design. Included in the technique is the ability to determine single redundant tests as well as multiple tests that are redundant to either other single or multiple tests. Once a potentially redundant test or group of tests arc identified, steps are be taken to determine whether the redundant test can be removed for the test sequence.