Patents by Inventor Ya-Chi HUNG
Ya-Chi HUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230395466Abstract: A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Harry-Haklay Chuang, Wen-Tuo Huang, Wei-Cheng Wu, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung
-
Publication number: 20230290748Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.Type: ApplicationFiled: June 15, 2022Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Wen-Tuo Huang, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung
-
Publication number: 20230268446Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Yu-Chun SHEN, Chi-Chung JEN, Ya-Chi HUNG, Yu-Chu LIN, Wen-Chih CHIANG
-
Patent number: 11682736Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.Type: GrantFiled: January 7, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chun Shen, Chi-Chung Jen, Ya-Chi Hung, Yu-Chu Lin, Wen-Chih Chiang
-
Publication number: 20230170249Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.Type: ApplicationFiled: May 6, 2022Publication date: June 1, 2023Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Chung-Jen Huang, Wen-Tuo Huang, Ya-Chi Hung, Chia-Sheng Lin
-
Publication number: 20230155036Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.Type: ApplicationFiled: January 23, 2023Publication date: May 18, 2023Inventors: Chi-Chung JEN, Ya-Chi HUNG, Yu-Chun SHEN, Shun-Neng WANG, Wen-Chih CHIANG
-
Patent number: 11563127Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.Type: GrantFiled: January 7, 2021Date of Patent: January 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Chung Jen, Ya-Chi Hung, Yu-Chun Shen, Shun-Neng Wang, Wen-Chih Chiang
-
Publication number: 20220216343Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.Type: ApplicationFiled: January 7, 2021Publication date: July 7, 2022Inventors: Yu-Chun SHEN, Chi-Chung JEN, Ya-Chi HUNG, Yu-Chu LIN, Wen-Chih CHIANG
-
Publication number: 20220216342Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.Type: ApplicationFiled: January 7, 2021Publication date: July 7, 2022Inventors: Chi-Chung JEN, Ya-Chi HUNG, Yu-Chun SHEN, Shun-Neng WANG, Wen-Chih CHIANG