Patents by Inventor Ya Chih Wang
Ya Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160379836Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.Type: ApplicationFiled: June 23, 2015Publication date: December 29, 2016Inventors: Chiang-Lin Shih, Shu-Hao Hsu, Ya-Chih Wang
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Patent number: 9530663Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.Type: GrantFiled: June 23, 2015Date of Patent: December 27, 2016Assignee: NANYA TECHNOLOGY CORP.Inventors: Chiang-Lin Shih, Shu-Hao Hsu, Ya-Chih Wang
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Patent number: 9318412Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.Type: GrantFiled: July 26, 2013Date of Patent: April 19, 2016Assignee: NANYA TECHNOLOGY CORPORATIONInventors: An Hsiung Liu, Ya Chih Wang
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Publication number: 20150028459Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.Type: ApplicationFiled: July 26, 2013Publication date: January 29, 2015Applicant: NANYA TECHNOLOGY CORPORATIONInventors: AN HSIUNG LIU, YA CHIH WANG
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Patent number: 8697316Abstract: A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.Type: GrantFiled: June 11, 2012Date of Patent: April 15, 2014Assignee: Nanya Technology Corp.Inventors: Ya-Chih Wang, Hai-Han Hung, Wen-Chieh Wang
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Patent number: 8658051Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.Type: GrantFiled: May 12, 2008Date of Patent: February 25, 2014Assignee: Nanya Technology Corp.Inventors: Kuo-Yao Cho, Wen-Bin Wu, Ya-Chih Wang, Chiang-Lin Shih, Chao-Wen Lay, Chih-Huang Wu
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Publication number: 20130330660Abstract: A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Inventors: Ya-Chih Wang, Hai-Han Hung, Wen-Chieh Wang
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Patent number: 8368869Abstract: A lithography apparatus with an optical fiber module includes: a light source, a photo mask positioned under the light source, a lens positioned under the photo mask, a wafer stage positioned under the lens for supporting the wafer, wherein the wafer includes a dry film. The lithography apparatus further includes an optical fiber module having a front surface facing away from the lens, wherein a gap is between the front surface and the dry film and the gap is smaller than the wavelength of the light source. The DUV (deep ultraviolet) can pass through the optical fiber module. The present invention features a gap smaller than the wavelength of the light source, creating a near-field effect with improved resolution.Type: GrantFiled: September 16, 2008Date of Patent: February 5, 2013Assignee: Nanya Technology Corp.Inventors: Wei-Cheng Shiu, Ya-Chih Wang
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Patent number: 8216946Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.Type: GrantFiled: June 23, 2009Date of Patent: July 10, 2012Assignee: Nanya Technology CorporationInventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
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Publication number: 20100323521Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.Type: ApplicationFiled: June 23, 2009Publication date: December 23, 2010Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
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Patent number: 7811723Abstract: A phase-shift mask for forming a pattern includes a glass substrate and a pattern, a first phase-shift region, a second phase-shift region and a third phase-shift region on the glass substrate. The first phase-shift region and the second phase-shift region are alternately arranged and the third phase-shift regions are formed at the terminal ends of the first phase-shift region.Type: GrantFiled: May 29, 2008Date of Patent: October 12, 2010Assignee: Nanya Technology Corp.Inventors: Kuo-Kuei Fu, Yuan-Hsun Wu, Ya-Chih Wang
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Patent number: 7799697Abstract: A patterning method in a semiconductor manufacturing process includes the following steps. A base is provided. A target layer and a lining layer are sequentially formed on the surface of the base. The lining layer is patterned to form a plurality of rectangular blocks. A sidewall spacer material layer is formed on the rectangular blocks and the target layer. Part of the sidewall spacer material layer is removed to form a sidewall spacer on the side wall of each of the plurality of rectangular blocks. The plurality of rectangular blocks is removed, and the sidewall spacer is used as a hard sheltering mask to etch and remove part of the target layer. The overlay accuracy is improved and the dimension of the electronic elements can be reduced so that a lot of two-dimension structures can be manufactured on the wafer substrate.Type: GrantFiled: May 13, 2008Date of Patent: September 21, 2010Assignee: Nanya Technology CorporationInventors: Wei-Cheng Shiu, Ya-Chih Wang
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Publication number: 20100020298Abstract: A lithography apparatus with an optical fiber module includes: a light source, a photo mask positioned under the light source, a lens positioned under the photo mask, a wafer stage positioned under the lens for supporting the wafer, wherein the wafer includes a dry film. The lithography apparatus further includes an optical fiber module having a front surface facing away from the lens, wherein a gap is between the front surface and the dry film and the gap is smaller than the wavelength of the light source. The DUV (deep ultraviolet) can pass through the optical fiber module. The present invention features a gap smaller than the wavelength of the light source, creating a near-field effect with improved resolution.Type: ApplicationFiled: September 16, 2008Publication date: January 28, 2010Inventors: Wei-Cheng Shiu, Ya-Chih Wang
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Publication number: 20090233448Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.Type: ApplicationFiled: May 12, 2008Publication date: September 17, 2009Applicant: NANYA TECHNOLOGY CORP.Inventors: Kuo-Yao CHO, Wen-Bin WU, Ya-Chih WANG, Chiang-Lin SHIH, Chao-Wen LAY, Chih-Huang WU
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Publication number: 20090227108Abstract: A patterning method in a semiconductor manufacturing process includes the following steps. A base is provided. A target layer and a lining layer are sequentially formed on the surface of the base. The lining layer is patterned to form a plurality of rectangular blocks. A sidewall spacer material layer is formed on the rectangular blocks and the target layer. Part of the sidewall spacer material layer is removed to form a sidewall spacer on the side wall of each of the plurality of rectangular blocks. The plurality of rectangular blocks is removed, and the sidewall spacer is used as a hard sheltering mask to etch and remove part of the target layer. The overlay accuracy is improved and the dimension of the electronic elements can be reduced so that a lot of two-dimension structures can be manufactured on the wafer substrate.Type: ApplicationFiled: May 13, 2008Publication date: September 10, 2009Inventors: Wei-Cheng Shiu, Ya-Chih Wang
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Publication number: 20090155699Abstract: A phase-shift mask for forming a pattern includes a glass substrate and a pattern, a first phase-shift region, a second phase-shift region and a third phase-shift region on the glass substrate. The first phase-shift region and the second phase-shift region are alternately arranged and the third phase-shift regions are formed at the terminal ends of the first phase-shift region.Type: ApplicationFiled: May 29, 2008Publication date: June 18, 2009Inventors: Kuo-Kuei Fu, Yuan-Hsun Wu, Ya-Chih Wang
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Patent number: 6998226Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35 ° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.Type: GrantFiled: July 10, 2002Date of Patent: February 14, 2006Assignee: Nanya Technology CorporationInventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang
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Publication number: 20030180666Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.Type: ApplicationFiled: July 10, 2002Publication date: September 25, 2003Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang