Patents by Inventor Ya Chih Wang

Ya Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160379836
    Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 29, 2016
    Inventors: Chiang-Lin Shih, Shu-Hao Hsu, Ya-Chih Wang
  • Patent number: 9530663
    Abstract: A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: December 27, 2016
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Chiang-Lin Shih, Shu-Hao Hsu, Ya-Chih Wang
  • Patent number: 9318412
    Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 19, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: An Hsiung Liu, Ya Chih Wang
  • Publication number: 20150028459
    Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 29, 2015
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: AN HSIUNG LIU, YA CHIH WANG
  • Patent number: 8697316
    Abstract: A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 15, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Ya-Chih Wang, Hai-Han Hung, Wen-Chieh Wang
  • Patent number: 8658051
    Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 25, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Kuo-Yao Cho, Wen-Bin Wu, Ya-Chih Wang, Chiang-Lin Shih, Chao-Wen Lay, Chih-Huang Wu
  • Publication number: 20130330660
    Abstract: A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Inventors: Ya-Chih Wang, Hai-Han Hung, Wen-Chieh Wang
  • Patent number: 8368869
    Abstract: A lithography apparatus with an optical fiber module includes: a light source, a photo mask positioned under the light source, a lens positioned under the photo mask, a wafer stage positioned under the lens for supporting the wafer, wherein the wafer includes a dry film. The lithography apparatus further includes an optical fiber module having a front surface facing away from the lens, wherein a gap is between the front surface and the dry film and the gap is smaller than the wavelength of the light source. The DUV (deep ultraviolet) can pass through the optical fiber module. The present invention features a gap smaller than the wavelength of the light source, creating a near-field effect with improved resolution.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: February 5, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Wei-Cheng Shiu, Ya-Chih Wang
  • Patent number: 8216946
    Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: July 10, 2012
    Assignee: Nanya Technology Corporation
    Inventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
  • Publication number: 20100323521
    Abstract: A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wei-Cheng Shiu, Hai-Han Hung, Ya-Chih Wang, Chien-Mao Liao, Shing-Yih Shih
  • Patent number: 7811723
    Abstract: A phase-shift mask for forming a pattern includes a glass substrate and a pattern, a first phase-shift region, a second phase-shift region and a third phase-shift region on the glass substrate. The first phase-shift region and the second phase-shift region are alternately arranged and the third phase-shift regions are formed at the terminal ends of the first phase-shift region.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: October 12, 2010
    Assignee: Nanya Technology Corp.
    Inventors: Kuo-Kuei Fu, Yuan-Hsun Wu, Ya-Chih Wang
  • Patent number: 7799697
    Abstract: A patterning method in a semiconductor manufacturing process includes the following steps. A base is provided. A target layer and a lining layer are sequentially formed on the surface of the base. The lining layer is patterned to form a plurality of rectangular blocks. A sidewall spacer material layer is formed on the rectangular blocks and the target layer. Part of the sidewall spacer material layer is removed to form a sidewall spacer on the side wall of each of the plurality of rectangular blocks. The plurality of rectangular blocks is removed, and the sidewall spacer is used as a hard sheltering mask to etch and remove part of the target layer. The overlay accuracy is improved and the dimension of the electronic elements can be reduced so that a lot of two-dimension structures can be manufactured on the wafer substrate.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: September 21, 2010
    Assignee: Nanya Technology Corporation
    Inventors: Wei-Cheng Shiu, Ya-Chih Wang
  • Publication number: 20100020298
    Abstract: A lithography apparatus with an optical fiber module includes: a light source, a photo mask positioned under the light source, a lens positioned under the photo mask, a wafer stage positioned under the lens for supporting the wafer, wherein the wafer includes a dry film. The lithography apparatus further includes an optical fiber module having a front surface facing away from the lens, wherein a gap is between the front surface and the dry film and the gap is smaller than the wavelength of the light source. The DUV (deep ultraviolet) can pass through the optical fiber module. The present invention features a gap smaller than the wavelength of the light source, creating a near-field effect with improved resolution.
    Type: Application
    Filed: September 16, 2008
    Publication date: January 28, 2010
    Inventors: Wei-Cheng Shiu, Ya-Chih Wang
  • Publication number: 20090233448
    Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.
    Type: Application
    Filed: May 12, 2008
    Publication date: September 17, 2009
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Kuo-Yao CHO, Wen-Bin WU, Ya-Chih WANG, Chiang-Lin SHIH, Chao-Wen LAY, Chih-Huang WU
  • Publication number: 20090227108
    Abstract: A patterning method in a semiconductor manufacturing process includes the following steps. A base is provided. A target layer and a lining layer are sequentially formed on the surface of the base. The lining layer is patterned to form a plurality of rectangular blocks. A sidewall spacer material layer is formed on the rectangular blocks and the target layer. Part of the sidewall spacer material layer is removed to form a sidewall spacer on the side wall of each of the plurality of rectangular blocks. The plurality of rectangular blocks is removed, and the sidewall spacer is used as a hard sheltering mask to etch and remove part of the target layer. The overlay accuracy is improved and the dimension of the electronic elements can be reduced so that a lot of two-dimension structures can be manufactured on the wafer substrate.
    Type: Application
    Filed: May 13, 2008
    Publication date: September 10, 2009
    Inventors: Wei-Cheng Shiu, Ya-Chih Wang
  • Publication number: 20090155699
    Abstract: A phase-shift mask for forming a pattern includes a glass substrate and a pattern, a first phase-shift region, a second phase-shift region and a third phase-shift region on the glass substrate. The first phase-shift region and the second phase-shift region are alternately arranged and the third phase-shift regions are formed at the terminal ends of the first phase-shift region.
    Type: Application
    Filed: May 29, 2008
    Publication date: June 18, 2009
    Inventors: Kuo-Kuei Fu, Yuan-Hsun Wu, Ya-Chih Wang
  • Patent number: 6998226
    Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35 ° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: February 14, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang
  • Publication number: 20030180666
    Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.
    Type: Application
    Filed: July 10, 2002
    Publication date: September 25, 2003
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang