Patents by Inventor Ya-Chin Hsu

Ya-Chin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure
    Patent number: 11978703
    Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
  • Unit-based layout system for passive IC devices
    Patent number: 7257794
    Abstract: A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnected instances of a device unit, such as a resistor segment or a capacitor block. User-supplied Input parameter values control the number of instances of the device unit included in the passive device layout, the relative positions of the device unit instances, and characteristics of their internal layouts. The tool also generates a display of a representation of the passive device layout and provides a graphical interface enabling the user to modify various aspects of the passive device layout by altering its displayed representation.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: August 14, 2007
    Assignee: Springsoft, Inc.
    Inventors: Shyh-An Tang, Ya-Chin Hsu
  • Unit-based layout system for passive IC devices
    Publication number: 20060136856
    Abstract: A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnected instances of a device unit, such as a resistor segment or a capacitor block. User-supplied Input parameter values control the number of instances of the device unit included in the passive device layout, the relative positions of the device unit instances, and characteristics of their internal layouts. The tool also generates a display of a representation of the passive device layout and provides a graphical interface enabling the user to modify various aspects of the passive device layout by altering its displayed representation.
    Type: Application
    Filed: January 19, 2005
    Publication date: June 22, 2006
    Inventors: Shyh-An Tang, Ya-Chin Hsu