Patents by Inventor Ya-Chin King
Ya-Chin King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210313472Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.Type: ApplicationFiled: June 17, 2021Publication date: October 7, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
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Patent number: 11043601Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.Type: GrantFiled: April 23, 2019Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
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Publication number: 20210159129Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.Type: ApplicationFiled: January 6, 2021Publication date: May 27, 2021Inventors: Burn-Jeng LIN, Chrong-Jung LIN, Ya-Chin KING, Yi-Pei TSAI
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Publication number: 20200395411Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
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Publication number: 20200321255Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.Type: ApplicationFiled: September 26, 2019Publication date: October 8, 2020Inventors: Burn-Jeng LIN, Chrong-Jung LIN, Ya-Chin KING, Yi-Pei TSAI
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Patent number: 10763305Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: September 18, 2018Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun Hsiao, Huang-Kui Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong-Jung Lin
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Publication number: 20190252552Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
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Patent number: 10276726Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.Type: GrantFiled: May 31, 2016Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
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Patent number: 10269437Abstract: A non-volatile memory device including a first floating-gate element, a second floating-gate element, and a selection gate element. The first floating-gate element includes a gate electrode configured to generate a read current based on the read voltage, the control voltage, and the electrical state of the gate electrode. The second floating-gate element shares a gate electrode with the first floating-gate element and is configured to determine the electrical state of the gate electrode based on the write voltage and the control voltage. The selection gate element is electrically coupled to the first floating-gate element and the second floating-gate element and is configured to generate the control voltage according to the word driving voltage and the source driving voltage.Type: GrantFiled: March 19, 2018Date of Patent: April 23, 2019Assignee: Copee Technology CompanyInventors: Chrong-Jung Lin, Ya-Chin King
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Publication number: 20190035850Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: September 18, 2018Publication date: January 31, 2019Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
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Publication number: 20180315481Abstract: A non-volatile memory device including a first floating-gate element, a second floating-gate element, and a selection gate element. The first floating-gate element includes a gate electrode configured to generate a read current based on the read voltage, the control voltage, and the electrical state of the gate electrode. The second floating-gate element shares a gate electrode with the first floating-gate element and is configured to determine the electrical state of the gate electrode based on the write voltage and the control voltage. The selection gate element is electrically coupled to the first floating-gate element and the second floating-gate element and is configured to generate the control voltage according to the word driving voltage and the source driving voltage.Type: ApplicationFiled: March 19, 2018Publication date: November 1, 2018Inventors: Chrong-Jung LIN, Ya-Chin KING
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Patent number: 10090360Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: October 16, 2015Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Woan-Yun Hsiao, Ya-Chin King, Chrong-Jung Lin, Huang-Kui Chen, Tzong-Sheng Chang
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Publication number: 20170345941Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
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Patent number: 9831130Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.Type: GrantFiled: June 9, 2017Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Lun Lo, Wei-Shuo Ho, Tzong-Sheng Chang, Chrong-Jung Lin, Ya-Chin King
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Patent number: 9805796Abstract: A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current, so as to generate a data-stored state signal.Type: GrantFiled: February 20, 2017Date of Patent: October 31, 2017Assignee: Copee Technology CompanyInventors: Chrong-Jung Lin, Ya-Chin King
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Publication number: 20170278570Abstract: A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current, so as to generate a data-stored state signal.Type: ApplicationFiled: February 20, 2017Publication date: September 28, 2017Inventors: Chrong-Jung LIN, Ya-Chin KING
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Publication number: 20170278756Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: An-Lun LO, Wei-Shuo HO, Tzong-Sheng CHANG, Chrong-Jung LIN, Ya-Chin KING
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Patent number: 9679818Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.Type: GrantFiled: October 31, 2014Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: An-Lun Lo, Wei-Shuo Ho, Tzong-Sheng Chang, Chrong-Jung Lin, Ya-Chin King
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Patent number: 9653469Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate.Type: GrantFiled: September 3, 2014Date of Patent: May 16, 2017Assignee: Copee Technology CompanyInventors: Chrong-Jung Lin, Ya-Chin King
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Publication number: 20160320445Abstract: A probeless parallel test system for an integrated circuit (IC) includes an IC chip, a wireless power receiving module and a Build-In Self-Test (BIST) circuit. The wireless power receiving module is electrically connected to the IC chip. The BIST circuit is electrically connected to the wireless power receiving module and the IC chip. The wireless power receiving module, the BIST circuit and the IC chip are all formed on a wafer. The wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip. When receiving the electric power, the IC chip executes a functional operation, and transmits an operation result to the BIST circuit for testing.Type: ApplicationFiled: July 7, 2015Publication date: November 3, 2016Inventors: Chrong-Jung LIN, Ya-Chin KING, Shi-Yu HUANG