Patents by Inventor Ya-Chun Tsai
Ya-Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12256543Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.Type: GrantFiled: February 10, 2022Date of Patent: March 18, 2025Assignee: MACRONIX International Co., Ltd.Inventors: Jung-Chuan Ting, Ya-Chun Tsai
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Patent number: 12218061Abstract: Methods, systems and apparatus for managing driving connection structures of memory devices, e.g., three-dimensional memory devices. In one aspect, a semiconductor device includes: a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure arranged between the first and second array structures along a first direction, and a circuit arranged adjacent to the connection structure. The connection structure includes: first and second connection areas through which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure configured to individually expose the first conductive layers in the first array structure, a second stepped structure configured to individually expose the second conductive layers in the second array structure.Type: GrantFiled: January 12, 2022Date of Patent: February 4, 2025Assignee: Macronix International Co., Ltd.Inventor: Ya-Chun Tsai
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Publication number: 20240379562Abstract: A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a top isolating member and a common wall, wherein the unprocessed region extends along the first direction, the staircase region is adjacent to a first side of the unprocessed region, the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region. The top isolating member extends along the first direction to separate the conductive layers disposed in a top portion of the stacked structure.Type: ApplicationFiled: July 19, 2024Publication date: November 14, 2024Inventor: Ya-Chun TSAI
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Patent number: 12087694Abstract: A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a bottom isolating member and a common wall, wherein the unprocessed region extends along the first direction and has an isolating sidewall, the isolating sidewall electrically isolates the conductive layers from the unprocessed region, the staircase region is adjacent to a first side of the unprocessed region, and the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region.Type: GrantFiled: March 1, 2022Date of Patent: September 10, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Ya-Chun Tsai
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Patent number: 11903194Abstract: In one embodiment of this disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad disposing area. The first memory block and the second memory block are respectively disposed at two sides of the integrated circuit, wherein each of the first memory block and the second memory block includes a memory cell array having a three-dimension structure. The first memory block and the second memory block are symmetrically disposed about the pad disposing area. A plurality of pads are disposed in the pad disposing area. The pads are respectively electrically coupled to the first memory block and the second memory block.Type: GrantFiled: November 17, 2021Date of Patent: February 13, 2024Assignee: MACRONIX International Co., Ltd.Inventor: Ya-Chun Tsai
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Publication number: 20230282584Abstract: A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a bottom isolating member and a common wall, wherein the unprocessed region extends along the first direction and has an isolating sidewall, the isolating sidewall electrically isolates the conductive layers from the unprocessed region, the staircase region is adjacent to a first side of the unprocessed region, and the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Inventor: Ya-Chun TSAI
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Publication number: 20230255028Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Jung-Chuan Ting, Ya-Chun Tsai
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Publication number: 20230223343Abstract: Methods, systems and apparatus for managing driving connection structures of memory devices, e.g., three-dimensional memory devices. In one aspect, a semiconductor device includes: a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure arranged between the first and second array structures along a first direction, and a circuit arranged adjacent to the connection structure. The connection structure includes: first and second connection areas through which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure configured to individually expose the first conductive layers in the first array structure, a second stepped structure configured to individually expose the second conductive layers in the second array structure.Type: ApplicationFiled: January 12, 2022Publication date: July 13, 2023Inventor: Ya-Chun Tsai
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Publication number: 20230157018Abstract: In one embodiment of this disclosure, an integrated circuit includes at least one first memory block, at least one second memory block, and a pad disposing area. The first memory block and the second memory block are respectively disposed at two sides of the integrated circuit, wherein each of the first memory block and the second memory block includes a memory cell array having a three-dimension structure. The first memory block and the second memory block are symmetrically disposed about the pad disposing area. A plurality of pads are disposed in the pad disposing area. The pads are respectively electrically coupled to the first memory block and the second memory block.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Applicant: MACRONIX International Co., Ltd.Inventor: Ya-Chun Tsai