Abstract: Disclosed herein is a novel apparatus and the uses thereof in the prophylaxis and/or treatment of neuropsychiatric disorders. The present apparatus comprises a detecting means, a stimulation means, a virtual reality means and a processor. According to some embodiments of the present disclosure, the present apparatus produces an additive or synergistic effect on the treatment of neuropsychiatric disorders.

Abstract: A digital signal processing apparatus comprises a main memory, a processing unit, a cache, and a rotate buffer unit. The main memory includes at least R memory banks for storing a plurality of data of digital signal. The cache is coupled between the main memory and the processing unit. The cache includes at least R×R cache units for storing part of data of the main memory to provide to the processing unit. The cache also temporarily stores operation results of the processing unit. The rotate buffer unit is coupled between the main memory and the cache for buffering and rotating the data outputted from each of the memory banks to write to the cache, and the data outputted from part of the cache units to write back to the corresponding memory banks respectively.

Abstract: A circuit, designed for supporting a computer system having a CPU, a monitor, and a system memory electrically connected to the CPU, includes a south bridge, and a north bridge electrically connected to the south bridge, the CPU, and the monitor. The north bridge includes a state machine and a graphics data buffer. When detecting that graphics data transferred by the graphics data buffer to the monitor is insufficient, the state machine sends a north bridge signal to the CPU to access inner data of the system memory.

Abstract: A digital signal processing apparatus comprises a main memory, a processing unit, a cache, and a rotate buffer unit. The main memory includes at least R memory banks for storing a plurality of data of digital signal. The cache is coupled between the main memory and the processing unit. The cache includes at least R×R cache units for storing part of data of the main memory to provide to the processing unit. The cache also temporarily stores operation results of the processing unit. The rotate buffer unit is coupled between the main memory and the cache for buffering and rotating the data outputted from each of the memory banks to write to the cache, and the data outputted from part of the cache units to write back to the corresponding memory banks respectively.

Abstract: A circuit, designed for supporting a computer system having a CPU, a monitor, and a system memory electrically connected to the CPU, includes a south bridge, and a north bridge electrically connected to the south bridge, the CPU, and the monitor. The north bridge includes a state machine and a graphics data buffer. When detecting that graphics data transferred by the graphics data buffer to the monitor is insufficient, the state machine sends a north bridge signal to the CPU to access inner data of the system memory.