Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.

Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.

Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.

Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.

Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.