Patents by Inventor YA-HUEI LI

YA-HUEI LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335601
    Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11742395
    Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20220216307
    Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11309217
    Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 11309213
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 11289578
    Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11222818
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
  • Publication number: 20200357691
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU
  • Publication number: 20200350414
    Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10727117
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20200020583
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiang CHAO, Min-Hsiu HUNG, Chun-Wen NIEH, Ya-Huei LI, Yu-Hsiang LIAO, Li-Wei CHU, Kan-Ju LIN, Kuan-Yu YEH, Chi-Hung CHUANG, Chih-Wei CHANG, Ching-Hwanq SU, Hung-Yi HUANG, Ming-Hsing TSAI
  • Publication number: 20190273024
    Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20190157141
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 23, 2019
    Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU