Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, and an etch buffer layer disposed over the sidewall spacers. The etch buffer layer includes an overhang component disposed on the upper portion of the sidewall spacers with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent sidewall spacers.

Abstract: A method for forming a pattern on a substrate is described. The method includes providing a substrate, forming a photosensitive layer over the substrate, exposing the photosensitive layer to a first exposure energy through a first mask, exposing the photosensitive layer to a second exposure energy through a second mask, baking the photosensitive layer, and developing the exposed photosensitive layer. The photosensitive layer includes a polymer that turns soluble to a developer solution, at least one photo-acid generator (PAG), and at least one photo-base generator (PBG). A portion of the layer exposed to the second exposure energy overlaps with a portion exposed to the first exposure energy.

Abstract: A card reader includes a control circuit, an audio transmission interface, and a conversion circuit. The control circuit is utilized to control data access of a smart card so as to read a first digital data from the smart card and write a second digital data to the smart card. The audio transmission interface is utilized to output a first analog audio signal and to receive a second analog audio signal. The conversion circuit is coupled to the control circuit and the audio transmission interface so as to convert the first digital data into the first analog audio signal and to convert the second analog audio signal into the second digital data.

Abstract: An electrical connector includes an insulating housing which has a base. Each side surface of the base protrudes outward to form a fixing block and a guiding block. A receiving groove is formed between the fixing block and the guiding block. A plurality of signal terminals are disposed in the insulating housing. A pair of positioning members each has a fixing board fastened in the fixing block. A front end of the fixing board extends frontward and then is arched oppositely to the base to form a flexible board elastically received in the receiving groove and has the apex project out of the receiving groove. When the electrical connector is inserted into the inserting mouth, the guiding block slips into the receiving fillister. The apex of the flexible board slips over the corresponding clipping element and then is restrained by the clipping element.

Abstract: Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.

Abstract: Provided is a lithography system that includes a source for providing energy, an imaging system configured to direct the energy onto a substrate to form an image thereon, and a diffractive optical element (DOE) incorporated with the imaging system, the DOE having a first dipole located in a first direction and a second dipole located in the first direction or a second direction perpendicular the first direction. The first dipole includes a first energy-transmitting region spaced a first distance from a center of the DOE. The second dipole includes a second energy-transmitting region spaced a second distance from the center of the DOE. The first distance is greater than the second distance.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.

Abstract: A gate driver structure of TFT-LCD display, comprising: a plurality of first level shifters, each input terminal of which being connected with an input signal; a plurality of output buffers with a plurality of output terminals, each input terminal of the output buffers being connected with each output terminal of the first level shifters; a second level shifter, the input terminal of which being connected with a low voltage signal and the first output terminal of which being connected with a plurality of first level shifters. In addition, the connecting wires between each output terminal of the plurality of first level shifters and each input terminal of the plurality of output buffers are in parallel with a pair of first MOS and second MOS daisy-chained together. The gate of each first MOS is connected with the output terminal of output buffer of the previous cell, and the gate of each second MOS is connected with the second output terminal of the second level shifter.

Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.

Abstract: Diagnosis of lung cancer based on the expression level(s) of one or more GTPase of Immunity-Associated Proteins (GIMAP) and method for identifying anti-lung cancer drug candidates based on their up-regulation of GIMAP activity.

Abstract: A gate driver structure of TFT-LCD display, comprising: a plurality of first level shifters, each input terminal of which being connected with an input signal; a plurality of output buffers with a plurality of output terminals, each input terminal of the output buffers being connected with each output terminal of the first level shifters; a second level shifter, the input terminal of which being connected with a low voltage signal and the first output terminal of which being connected with a plurality of first level shifters. In addition, the connecting wires between each output terminal of the plurality of first level shifters and each input terminal of the plurality of output buffers are in parallel with a pair of first MOS and second MOS daisy-chained together. The gate of each first MOS is connected with the output terminal of output buffer of the previous cell, and the gate of each second MOS is connected with the second output terminal of the second level shifter.

Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.

Abstract: The invention relates to a judgment apparatus for determining the size of a document. The judgment apparatus includes an automatic document feeding (ADF) with a scan window, a scanner carriage, and a decision module. The ADF transmits the document. The scanner carriage determines a first dimension of the scan window masked by the document, and outputs the first size. The decision module determines the size of the document according to the first dimension output by the scanner carriage.

Abstract: This invention features a marker set that includes different microsatellite markers corresponding respectively to different genetic loci, wherein a heterozygosity value for each genetic locus is at least 0.50 in the Mongoloid population, and the genetic distance between two adjacent microsatellite markers is in the average of 10 cM.

Abstract: This method comprising a stop layer, a dielectric layer, a bottom hard layer and top hard mask layer are formed on a substrate, sequentially. A via pattern photoresist layer is formed on the top hard mask layer. The top hard mask layer is etched by using the via pattern photoresist layer as a mask to transfer the via pattern into the top hard mask layer then removed the via pattern photoresist layer. A trench pattern photoresist layer is formed on the top hard mask layer wherein the trench pattern is over the via pattern. The bottom hard mask layer is etched by using the top hard mask layer as a mask to transfer the via pattern into the bottom hard mask layer. The top hard mask layer is etched by using the trench pattern photoresist layer as a mask, wherein the via pattern is transferred into a portion of the dielectric layer. The bottom hard mask layer is etched by using the top hard mask layer as a mask, wherein the via pattern is transferred into the dielectric layer.

Abstract: In accordance with the present invention, a method is provided for improving process photolithography resolution of narrow pitch patterning. The alternate exposure method for improving photolithography resolution of an original pattern with a first pitch, wherein the original pattern is a combination of a plurality of split patterns, comprises the step of providing a substrate having a layer of photoresist formed thereon. Then, a plurality of reticles having the plurality of split patterns with a second pitch is provided, wherein the second pitch is larger than the first pitch. Next, a plurality of exposures is successively performed to form a plurality of exposure regions of the plurality of split patterns in the photoresist layer using the plurality of reticles. The original pattern is transferred into the photoresist layer by combining the plurality of exposure regions of the plurality of split patterns. And then, a development of the photoresist layer is performed.