Abstract: A pixel circuit is provided. In the pixel circuit, a first transistor has a first terminal coupled to a first node and a second terminal receiving a system high voltage, and the first transistor is controlled by a light emitting signal. A first terminal and a second terminal of a second transistor are respectively coupled to a second node and the first node; a control terminal of the second transistor is coupled to a third node. The third transistor is coupled between the first node and the third node and controlled by a first scan signal. A capacitor has a first terminal and a second terminal. A voltage setting circuit receives a data signal, a second scan signal, and a third scan signal. A first terminal of the light emitting device is coupled to the second node; a second terminal of the light emitting device receives a system low voltage.

Abstract: An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.

Abstract: A method of manufacturing a pixel structure of a liquid crystal display panel includes providing a substrate, forming a pixel electrode and a switch device that is electrically connected to the pixel electrode on the substrate, forming an insulating layer that covers the switch device and the pixel electrode on the substrate, forming a common electrode layer on the insulating layer, forming a patterned photoresist layer that includes a plurality of discontinuous patterns on the common electrode layer, performing a first etching process to remove a portion of the common electrode layer so as to forma patterned common electrode, performing a second etching process to remove part of a surface of the insulating layer so as to form a plurality of trenches, wherein the patterned common electrode does not cover the plurality of trenches, and removing the patterned photoresist layer.

Abstract: An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A method of manufacturing a pixel structure of a liquid crystal display panel includes providing a substrate, forming a pixel electrode and a switch device that is electrically connected to the pixel electrode on the substrate, forming an insulating layer that covers the switch device and the pixel electrode on the substrate, forming a common electrode layer on the insulating layer, forming a patterned photoresist layer that includes a plurality of discontinuous patterns on the common electrode layer, performing a first etching process to remove a portion of the common electrode layer so as to forma patterned common electrode, performing a second etching process to remove part of a surface of the insulating layer so as to form a plurality of trenches, wherein the patterned common electrode does not cover the plurality of trenches, and removing the patterned photoresist layer.

Abstract: A pixel structure of a liquid crystal display panel includes a substrate, a switch device, a pixel electrode, an insulating layer, and a patterned common electrode. The switch device and the pixel electrode are disposed on the substrate, and the switch device is electrically connected to the pixel electrode. The insulating layer is disposed on the substrate and covers the switch device and the pixel electrode, wherein the insulating layer includes a plurality of trenches. The patterned common electrode is disposed on the insulating layer and does not cover the trenches. The pixel structure of the liquid crystal display panel and related manufacturing method are able to enhance the driving effect of the liquid crystal molecules, reduce the driving voltage and increase alignment performance of the alignment film.

Abstract: A pixel structure of a liquid crystal display panel includes a substrate, a switch device, a pixel electrode, an insulating layer, and a patterned common electrode. The switch device and the pixel electrode are disposed on the substrate, and the switch device is electrically connected to the pixel electrode. The insulating layer is disposed on the substrate and covers the switch device and the pixel electrode, wherein the insulating layer includes a plurality of trenches. The patterned common electrode is disposed on the insulating layer and does not cover the trenches. The pixel structure of the liquid crystal display panel and related manufacturing method are able to enhance the driving effect of the liquid crystal molecules, reduce the driving voltage and increase alignment performance of the alignment film.

Abstract: The invention provides an active device and a manufacturing method thereof, the active device disposed on a substrate includes a gate, a gate insulating layer, a metal oxide semiconductor layer, an etch stop layer, a source, and a drain. The gate insulating layer is disposed on the substrate and covers the gate. The metal oxide semiconductor layer is disposed on the gate insulating layer. The etch stop layer is disposed on the metal oxide semiconductor layer. The edges of the metal oxide semiconductor layer are retracted a distance compared to the edges of the etch stop layer. The source and the drain are disposed on the etch stop layer, disposed along the edges of the etch stop layer and the edges of the metal oxide semiconductor layer, and extendedly disposed on the gate insulating layer. A part of the etch stop layer is exposed between the source and the drain.

Abstract: A manufacturing method of a thin film transistor includes the following steps. A substrate is provided first. A semiconductor layer is then formed on the substrate. Next, a photoresist pattern including a middle portion and two peripheral portions is formed on the semiconductor layer. The middle portion is disposed between two peripheral portions, and the thickness of the middle portion is greater than each of the peripheral portions. Next, an etching process is performed on the semiconductor layer for forming a patterned semiconductor layer. A photoresist ashing process is then performed to remove at least the peripheral portions of the photoresist pattern to form a channel defining photoresist pattern and expose two portions of the patterned semiconductor layer. Next, the patterned semiconductor layer is treated to form a semiconductor portion and two conductor portions. The channel defining photoresist pattern is then removed.

Abstract: A double thin film transistor includes a first semiconductor layer, a gate, a second semiconductor layer, a first insulating layer, a second insulating layer, a first source, a first drain, a second source and a second drain. The first semiconductor layer is disposed over a substrate. The gate is disposed over the first semiconductor layer. The second semiconductor layer is disposed over the gate, and the first and second semiconductor layers are the same conductive type. The first insulating layer is disposed between the first semiconductor layer and the gate. The second insulating layer is disposed between the gate and the second semiconductor layer. The first source and the first drain are disposed between the substrate and the second insulating layer. The second source and the second drain are disposed over the second insulating layer.

Abstract: The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance.

Abstract: A manufacturing method of a thin film transistor includes the following steps. A substrate is provided first. A semiconductor layer is then formed on the substrate. Next, a photoresist pattern including a middle portion and two peripheral portions is formed on the semiconductor layer. The middle portion is disposed between two peripheral portions, and the thickness of the middle portion is greater than each of the peripheral portions. Next, an etching process is performed on the semiconductor layer for forming a patterned semiconductor layer. A photoresist ashing process is then performed to remove at least the peripheral portions of the photoresist pattern to form a channel defining photoresist pattern and expose two portions of the patterned semiconductor layer. Next, the patterned semiconductor layer is treated to form a semiconductor portion and two conductor portions. The channel defining photoresist pattern is then removed.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A double thin film transistor includes a first semiconductor layer, a gate, a second semiconductor layer, a first insulating layer, a second insulating layer, a first source, a first drain, a second source and a second drain. The first semiconductor layer is disposed over a substrate. The gate is disposed over the first semiconductor layer. The second semiconductor layer is disposed over the gate, and the first and second semiconductor layers are the same conductive type. The first insulating layer is disposed between the first semiconductor layer and the gate. The second insulating layer is disposed between the gate and the second semiconductor layer. The first source and the first drain are disposed between the substrate and the second insulating layer. The second source and the second drain are disposed over the second insulating layer.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

Abstract: A manufacturing method of a pixel structure is provided, which includes following steps. A gate and a gate insulating layer are formed on a substrate. A source and a drain are formed on the gate insulating layer. A first and a second semiconductor pattern are formed on the gate insulating layer. The first semiconductor pattern is located above the gate, wherein the first semiconductor pattern contacts the source and the drain. The second semiconductor pattern contacts the drain. A mask which exposes both sides of the first semiconductor pattern is formed on the first semiconductor pattern. A treatment procedure is performed, so that a first and a second conductive region are formed at both sides of the exposed first semiconductor pattern, and the second semiconductor pattern is formed into a pixel electrode pattern. The first semiconductor pattern which is covered by the mask is formed into a channel region.

Abstract: The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance.

Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain, A TFT is also provided.

Abstract: A thin film transistor disposed above a carrying surface of a substrate is provided. The thin film transistor includes a gate, a first insulation layer, a channel, a source, a second insulation layer and a drain. The gate and the channel are overlapped with each other in a normal direction of the carrying surface. The first insulation layer is disposed between the channel and the gate. The source covers a portion of the channel and is electrically connected to the portion of the channel. The channel is located between the source and the first insulation layer in the normal direction. The source is disposed between the second insulation layer and the channel. The second insulation layer has a first hole exposing another portion of the channel. The drain is filled in the first hole and electrically connected to the another portion of the channel. Moreover, a pixel structure is provided.