Patents by Inventor Ya-Jui Tsou
Ya-Jui Tsou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250133968Abstract: The present invention provides a spin-orbit torque magnetoresistive memory structure, which comprises a first conductive layer, a magnetic tunneling junction (MTJ) layer, a channel layer, and a second conductive layer stacked sequentially. The MTJ layer is disposed on the first conductive layer. The channel layer is disposed on the MTJ layer. The second conductive layer is disposed on the channel layer. These structures are fabricated sequentially using lithography. By forming the MTJ layer before the channel layer, redeposition of the metal of the channel layer on the MTJ layer can be avoided.Type: ApplicationFiled: October 21, 2024Publication date: April 24, 2025Inventors: Ya-Jui Tsou, Duan-Lee Tang, Yuan-Chen Sun, Kai-Shin Li, Ya-Ling Wu, Jia-Min Shieh
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Publication number: 20250056812Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.Type: ApplicationFiled: October 30, 2024Publication date: February 13, 2025Inventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
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Patent number: 12160998Abstract: The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.Type: GrantFiled: July 22, 2022Date of Patent: December 3, 2024Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Zong-You Luo, Ya-Jui Tsou, I-Cheng Tung, CheeWee Liu
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Publication number: 20240355912Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.Type: ApplicationFiled: July 1, 2024Publication date: October 24, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Wei-Jen CHEN, Pang-Chun LIU, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
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Publication number: 20240341200Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.Type: ApplicationFiled: June 20, 2024Publication date: October 10, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Wei-Jen CHEN, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
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Patent number: 12100737Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: GrantFiled: July 26, 2023Date of Patent: September 24, 2024Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Patent number: 12069965Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.Type: GrantFiled: July 17, 2023Date of Patent: August 20, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Patent number: 12062713Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.Type: GrantFiled: April 7, 2022Date of Patent: August 13, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Wei-Jen Chen, Pang-Chun Liu, Chee-Wee Liu, Shao-Yu Lin, Chih-Lin Wang
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Patent number: 12052934Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.Type: GrantFiled: February 10, 2022Date of Patent: July 30, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Wei-Jen Chen, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Chih-Lin Wang
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Publication number: 20240212732Abstract: A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.Type: ApplicationFiled: March 8, 2024Publication date: June 27, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chia-Che CHUNG, Chia-Jung TSEN, Ya-Jui TSOU, Chee-Wee LIU
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Patent number: 11967351Abstract: A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.Type: GrantFiled: April 12, 2022Date of Patent: April 23, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chia-Che Chung, Chia-Jung Tsen, Ya-Jui Tsou, Chee-Wee Liu
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Publication number: 20230397501Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Jih-Chao CHIU, Huan-Chi SHIH, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
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Publication number: 20230369407Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Publication number: 20230363287Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui TSOU, Zong-You LUO, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Publication number: 20230360686Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You LUO, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Liang-Chor CHUNG, Chih-Lin WANG
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Patent number: 11778923Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.Type: GrantFiled: November 14, 2021Date of Patent: October 3, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Zong-You Luo, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Patent number: 11749328Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.Type: GrantFiled: July 25, 2022Date of Patent: September 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Zong-You Luo, Ya-Jui Tsou, Chee-Wee Liu, Shao-Yu Lin, Liang-Chor Chung, Chih-Lin Wang
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Patent number: 11742388Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.Type: GrantFiled: July 22, 2022Date of Patent: August 29, 2023Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Ya-Jui Tsou, Zong-You Luo, Wen Hung Huang, Jhih-Yang Yan, Chee-Wee Liu
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Publication number: 20230255122Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Wei-Jen CHEN, Ya-Jui TSOU, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
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Publication number: 20230170403Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.Type: ApplicationFiled: April 7, 2022Publication date: June 1, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Ya-Jui Tsou, Wei-Jen Chen, Pang-Chun Liu, Chee-Wee Liu, Shao-Yu Lin, Chih-Lin Wang