Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

Abstract: A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.

Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.

Abstract: An engineering analysis tool comprises a unified resource model-based (URM) objective and tool mapping capability for linking engineering analysis objectives to analysis tools. A Markov chain-based analysis plan generator (APTG) for reusing engineering analysis plans may be included in the engineering analysis tool. Further, the engineering analysis tool comprises a graphic symptom capturer (GSC) that auto-captures engineering perceived fault symptoms from engineering data analysis (EDA) tools.

Abstract: An engineering analysis tool comprises a unified resource model-based (URM) objective and tool mapping capability for linking engineering analysis objectives to analysis tools. A Markov chain-based analysis plan generator (APTG) for reusing engineering analysis plans may be included in the engineering analysis tool. Further, the engineering analysis tool comprises a graphic symptom capturer (GSC) that auto-captures engineering perceived fault symptoms from engineering data analysis (EDA) tools.