Patents by Inventor Yaping Chen

Yaping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230212611
    Abstract: The present disclosure relates generally to a molecular delivery system and methods of using the molecular delivery system to deliver biomolecules into cells. In particular, the molecular delivery system comprises a nanotube (NT) array comprising a plurality of nanotubes (NTs) which are used to deliver biomolecules to cells. The NTs can be loaded with molecules that can be delivered into cells following contact (e.g. penetration) by the NTs.
    Type: Application
    Filed: February 10, 2021
    Publication date: July 6, 2023
    Inventors: Nicolas Hans VOELCKER, Roey ELNATHAN, Stella ASLANOGLOU, Yaping CHEN
  • Patent number: 10573553
    Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Abbas Ali, Yaping Chen, Chao Zuo, Seetharaman Sridhar, Yunlong Liu
  • Patent number: 10417372
    Abstract: Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells in the power intent specification. The correspondence can be stored in a memory of a computer, and can be used for annotating a visual representation of a signal in a circuit design view based on a corresponding isolation cell. Next, the circuit design view with the annotated visual representation of the signal can be displayed.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: September 17, 2019
    Assignee: Synopsys, Inc.
    Inventors: Chih Neng Hsu, Yaping Chen
  • Publication number: 20190157142
    Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 23, 2019
    Inventors: Hong YANG, Abbas ALI, Yaping CHEN, Chao ZUO, Seetharaman SRIDHAR, Yunlong LIU
  • Patent number: 10211096
    Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hong Yang, Abbas Ali, Yaping Chen, Chao Zuo, Seetharaman Sridhar, Yunlong Liu
  • Publication number: 20170279321
    Abstract: A steel magnet body assembly comprises a first magnetizer (1) and a second magnetizer (2) that are magnetically conductive, and comprises multiple steel magnets (3). A magnetically insulative fixing member (4) used for fixing the steel magnets (3) is disposed between the first magnetizer (1) and the second magnetizer (2). The first magnetizer (1), the fixing member (4) and the second magnetizer (2) are sequentially stacked. The multiple steel magnets (3) are fixed in the fixing member (4) in an evenly spaced manner. Each steel magnet (3) is a column having an N magnetic pole and an S magnetic pole, and the N magnetic pole and the S magnetic pole of the steel magnets (3) are relatively disposed on two sides of a plane where the central axis of the column of the steel magnet (3) is located.
    Type: Application
    Filed: August 28, 2014
    Publication date: September 28, 2017
    Inventors: Shugang GONG, Shiwei HU, Yaping CHEN, Jigao ZHAO, Changliang LI
  • Publication number: 20170147720
    Abstract: Systems and techniques for creating and displaying a circuit design view are described. A hardware description language (HDL) specification and a power intent specification of the circuit design can be analyzed to determine a correspondence between one or more signals in the HDL specification and one or more isolation cells in the power intent specification. The correspondence can be stored in a memory of a computer, and can be used for annotating a visual representation of a signal in a circuit design view based on a corresponding isolation cell. Next, the circuit design view with the annotated visual representation of the signal can be displayed.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Applicant: Synopsys, Inc.
    Inventors: Chih Neng Hsu, Yaping Chen
  • Patent number: 6197568
    Abstract: Methods and compositions for the isolation, diagnosis and treatment of microorganisms such as flaviviruses and other hemorrhagic fever viruses are based on the sulfated polyanion-dependent interaction of flaviviruses and hemorrhagic fever viruses, in particular dengue virus, with target cells. The cellular receptors targeted by these viruses have been identified as sulfated polyanionic glycoproteins, that include highly sulfated heparan sulfate glycosaminoglycans for some target cell types, and as a sulfated mucin on vascular endothelium. Compounds such as heparin, highly sulfated heparan sulfate, and synthetic polyanions such as Suramin, inhibit the interaction between the microorganisms and target cells, thereby disrupting the infective process.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: March 6, 2001
    Assignee: The Regents of the University of Michigan
    Inventors: Rory M. Marks, Yaping Chen, Terence Maguire, Robert J. Linhardt
  • Patent number: D914548
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 30, 2021
    Assignee: Foshan Zhengbu Technology Co., Ltd.
    Inventor: Yaping Chen
  • Patent number: D914549
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 30, 2021
    Assignee: Foshan Zhengbu Technology Co., Ltd.
    Inventor: Yaping Chen
  • Patent number: D933538
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: October 19, 2021
    Assignee: Foshan Zhengbu Technology Co., Ltd.
    Inventor: Yaping Chen
  • Patent number: D991839
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: July 11, 2023
    Assignee: Foshan Zhengbu Technology Co., Ltd.
    Inventor: Yaping Chen
  • Patent number: D1008886
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: December 26, 2023
    Assignee: Foshan Zhengbu Technology Co., Ltd.
    Inventor: Yaping Chen