Abstract: A semiconductor package comprise: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a set of front conductive patterns formed on the front surface; a set of rear conductive patterns formed on the rear surface; and a set of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; at least one electronic component mounted on the front surface of the package substrate and electrically coupled to the set of front conductive patterns via a set of front solder balls; a set of rear solder balls electrically connected to the set of rear conductive patterns, respectively; wherein the set of front solder balls comprises one or more first-type solder balls and one or more second-type solder balls, and the set of rear solder balls comprises one or more first-type solder balls and one or more second-type solder balls; and wherein the first-type solder balls of the set of front solder balls are elec

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; a plurality of electronic components mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the plurality sets of conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the set of first-type conductive components are connected to a first electronic component of the plurality of electronic components, and the set of second-type conductive components are connected to a second electronic component of the plurality of electronic components; and wherein

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns; a plurality sets of rear conductive patterns; and a plurality sets of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; wherein the package substrate at least comprises a first thermal performance region and a second thermal performance region, wherein the first thermal performance region and the second thermal performance region have different thermal performances; a plurality sets of conductive components attached to the front surface and the rear surface of the package substrate and connected to the plurality sets of front conductive patterns and the plurality sets of rear conductive patterns, wherein the plurality sets of conductive components comprise: a set of first-type conductive components mounted to the first thermal performance region of

Abstract: A wand includes a hinge configured to pivotally connect first and second wand segments in an extended configuration and a storage configuration. A first locking mechanism locks the wand in extended configuration. A second locking mechanism includes a rod, a sliding lever, a plunger, and a plunger cavity. The plunger is configured to be received in the plunger cavity to lock the wand in the storage configuration. When in the extended configuration, depressing a single actuator pivots the locking arm, causes the hook/pawl to be removed from the locking cavity, and unlocks the wand. When in the storage configuration, depressing the single actuator causes the rod to move in a first direction, causes the sliding rod to move a second direction, and urges the plunger out of the plunger cavity.

Abstract: Disclosed are a connection line structure and a forming method thereof. The connection line structure includes a passivation layer, a metal layer, and a protective layer, the metal layer is arranged on the passivation layer, and the protective layer is arranged on the metal layer. In the present application, a simple single-layer wiring design may be utilized, and a multi-layer three-dimensional wiring design may also be utilized to implement high speed transmission, a MEMS process allows for design of a connection line in a straight or bent layout, a connection line of a bent layout is flexible, and better compatibility is achieved.

Abstract: A wand includes a hinge configured to pivotally connect first and second wand segments in an extended configuration and a storage configuration. A first locking mechanism locks the wand in extended configuration. A second locking mechanism includes a rod, a sliding lever, a plunger, and a plunger cavity. The plunger is configured to be received in the plunger cavity to lock the wand in the storage configuration. When in the extended configuration, depressing a single actuator pivots the locking arm, causes the hook/pawl to be removed from the locking cavity, and unlocks the wand. When in the storage configuration, depressing the single actuator causes the rod to move in a first direction, causes the sliding rod to move a second direction, and urges the plunger out of the plunger cavity.

Abstract: The present invention provides a manufacturing method of a semiconductor packaging member, a semiconductor packaging member and a mounting method thereof. The manufacturing method includes the following steps of: pre-molding packaging a lead frame, forming a pre-molding package body both between a lead and a base, and between two adjacent leads in each lead frame unit; forming a groove by thinning an outer lead from a front surface of the outer lead; forming a tin block in the groove; mounting a chip on the base island; plastic-packaging the lead frame which has completed the wire-bonded; forming a semifinished product by forming a tin-plated layer in an exposed region of a back surface of the plastic-packaged lead frame; and forming a single semiconductor packaging member by cutting the semifinished product, the tin block in the semiconductor packaging member is exposed away from the base island.

Abstract: A wand includes a hinge configured to pivotally connect first and second wand segments in an extended configuration and a storage configuration. A first locking mechanism locks the wand in extended configuration. A second locking mechanism includes a rod, a sliding lever, a plunger, and a plunger cavity. The plunger is configured to be received in the plunger cavity to lock the wand in the storage configuration. When in the extended configuration, depressing a single actuator pivots the locking arm, causes the hook/pawl to be removed from the locking cavity, and unlocks the wand. When in the storage configuration, depressing the single actuator causes the rod to move in a first direction, causes the sliding rod to move a second direction, and urges the plunger out of the plunger cavity.

Abstract: Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.

Abstract: A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).

Abstract: Provided is an etching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with a chip. The structure comprises a metal substrate frame, wherein a base island and pins are arranged in the metal substrate frame; a chip is inversely arranged on a front face of the base island and the pins; a conductive pillar is arranged on a front face of the pins; the region on the periphery of the base island, the region between the base island and the pins, the region between one pin and another, the region above the base island and the pins, the region below the base island and the pins, and the outside of the chip and the conductive pillar are all enveloped with a plastic packaging material.

Abstract: A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).

Abstract: Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.

Abstract: Provided is an etching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with a chip. The structure comprises a metal substrate frame, wherein a base island and pins are arranged in the metal substrate frame; a chip is inversely arranged on a front face of the base island and the pins; a conductive pillar is arranged on a front face of the pins; the region on the periphery of the base island, the region between the base island and the pins, the region between one pin and another, the region above the base island and the pins, the region below the base island and the pins, and the outside of the chip and the conductive pillar are all enveloped with a plastic packaging material.

Abstract: Provided are a packaging-before-etching flip chip 3D system-level metal circuit board structure and technique thereof. The metal circuit board structure comprises a metal substrate frame; the front face of the metal substrate frame is provided with pins; the front faces of the pins are provided with conductive posts; chips are installed in a flip manner between the pins via underfills; the peripheral areas of the pins, the conductive posts and the chip are encapsulated with molding compound, the top of the molding compound being parallel to the tops of the conductive posts; and the surfaces of the metal substrate frame, the pins and the conductive posts exposing out of the molding compounds are provided with an anti-oxidation layer, thus solving the problem of limited functionality and application of a traditional metal lead frame due to the fact that objects cannot be embedded therein.

Abstract: The present invention relates to a first-packaged and later-etched normal chip three dimension-on-chip metal circuit board structure and a processing method for manufacturing the same, the structure includes: metal substrate frame (1); a lead (3) provided in the metal substrate frame (1); a conductive pillar (4) provided in a top surface of the lead (3); a chip is mounted normally on a top surface of the metal circuit frame (1) or between the leads (3); a metal wire (6) via which a top surface of the chip (5) is connected to a top surface of the lead (3); a molding material (8) with which a periphery region of the lead (3), the conductive pillar (4), the chip (5) and the metal wire (6) is encapsulated, with the molding material (8) being flushed with a top of the conductive pillar (4).