Abstract: A display method and a display system for an anti-dizziness reference image are provided. The display system includes a display, a range extraction unit, an information analyzing unit, an object analyzing unit and an image setting unit. The display is used to display the anti-dizziness reference image. The range extraction unit is used to obtain a gaze background range of a user. The image setting unit is used to set an image hue, an image lightness, an image brightness, an image content or an ambient lighting display content of the anti-dizziness reference image according to a background hue information, a background lightness information, a background brightness information, or a road information of the gaze background range; or set an image ratio between the anti-dizziness reference image and a display area of the display according to an object distance or an object area of the watched object.

Abstract: A pixel array substrate includes a display area, signal lines, transmission lines, selection lines, and jumper wires. The selection lines intersect with the signal lines to form intersection regions. The selection lines have first contacts, second contacts, and third contacts. The first contacts are respectively located on the intersection regions. Each of the first contacts is between one of the second contacts and one of the third contacts. A first portion of the first contacts are passed by a line of the display area. The jumper wires respectively pass the first contacts, and two ends of each of the jumper wires are respectively located on one of the second contacts and one of the third contacts. A first portion of the jumper wires electrically connect the first portion of the first contacts and the second contacts, but electrically isolate the third contacts.

Abstract: A pixel array substrate includes a display area, signal lines, transmission lines, selection lines, and jumper wires. The selection lines intersect with the signal lines to form intersection regions. The selection lines have first contacts, second contacts, and third contacts. The first contacts are respectively located on the intersection regions. Each of the first contacts is between one of the second contacts and one of the third contacts. A first portion of the first contacts are passed by a line of the display area. The jumper wires respectively pass the first contacts, and two ends of each of the jumper wires are respectively located on one of the second contacts and one of the third contacts. A first portion of the jumper wires electrically connect the first portion of the first contacts and the second contacts, but electrically isolate the third contacts.

Abstract: An active matrix substrate includes a substrate and an insulating unit arranged on the substrate. The substrate includes a display region and a periphery circuit region beside the display region. The periphery circuit region has at least a chip connecting unit. Each chip connecting unit includes a number of connecting elements. Each of the connecting elements includes a conducting pad and a wire electrically connected to the conducting pad. The conducting pads of the connecting elements are arranged in at least two rows. The insulating unit has a number of contact holes corresponding to the conducting pads so that each of the conducting pads is entirely exposed by the corresponding contact hole. The active matrix substrate is applied to a display device to increase reliability of the display device and improve the quality of the display device.

Abstract: A display panel includes a first substrate, a display layer, a second substrate and a water-proofing frame. The first substrate has a view area and a ring-shaped through trench and includes a first base, a first metal layer, a gate-insulating layer, a second metal layer, a semiconductor layer, a bibulous insulating layer and a pixel-electrode layer. The gate-insulating layer is disposed between the first and the second metal layers. The bibulous insulating layer is disposed on the second metal layer and the gate-insulating layer. The ring-shaped through trench passes through the bibulous insulating layer and the part of the gate-insulating layer exposed by the second metal layer and surrounds the view area. The water-proofing frame is disposed at the ring-shaped through trench, connects the first substrate and the second substrate and encloses a wet-proof space between the first substrate and the second substrate. Besides, another display panel is also provided.

Abstract: An active matrix substrate includes a substrate and an insulating unit arranged on the substrate. The substrate includes a display region and a periphery circuit region beside the display region. The periphery circuit region has at least a chip connecting unit. Each chip connecting unit includes a number of connecting elements. Each of the connecting elements includes a conducting pad and a wire electrically connected to the conducting pad. The conducting pads of the connecting elements are arranged in at least two rows. The insulating unit has a number of contact holes corresponding to the conducting pads so that each of the conducting pads is entirely exposed by the corresponding contact hole. The active matrix substrate is applied to a display device to increase reliability of the display device and improve the quality of the display device.

Abstract: A pin definition layout of electronic paper display screen is provided. The electronic paper has a first pin area, a data signal source driver area, and a second pin area sequentially disposed at any side thereof. The first pin area and the second pin area each have a first power supply pin set and a second power supply pin set disposed thereon, and a plurality of No connections is disposed by intervals in the first power supply pin set and the second power supply pin set, so as to separate potential pins. Therefore, no interference is generated between the pins, thus achieving good electrical properties and reducing the wire complexity.

Abstract: An electrophoresis display apparatus has a display circuit and a voltage source. The display circuit comprises a gate line, a common voltage line substantially orthogonal to the gate line, a data line and a display unit. The gate line provides a gate voltage, the common voltage line provides a common voltage, and the data line provides a data voltage. The display unit is coupled to the gate line, the common voltage line and the data line to receive the gate voltage, the common voltage and the data line and works according to the gate voltage, the common voltage and the data line.

Abstract: A display panel includes a first substrate, a display layer, a second substrate and a water-proofing frame. The first substrate has a view area and a ring-shaped through trench and includes a first base, a first metal layer, a gate-insulating layer, a second metal layer, a semiconductor layer, a bibulous insulating layer and a pixel-electrode layer. The gate-insulating layer is disposed between the first and the second metal layers. The bibulous insulating layer is disposed on the second metal layer and the gate-insulating layer. The ring-shaped through trench passes through the bibulous insulating layer and the part of the gate-insulating layer exposed by the second metal layer and surrounds the view area. The water-proofing frame is disposed at the ring-shaped through trench, connects the first substrate and the second substrate and encloses a wet-proof space between the first substrate and the second substrate. Besides, another display panel is also provided.

Abstract: A pin definition layout of electronic paper display screen is provided. The electronic paper has a first pin area, a data signal source driver area, and a second pin area sequentially disposed at any side thereof. The first pin area and the second pin area each have a first power supply pin set and a second power supply pin set disposed thereon, and a plurality of No connections is disposed by intervals in the first power supply pin set and the second power supply pin set, so as to separate potential pins. Therefore, no interference is generated between the pins, thus achieving good electrical properties and reducing the wire complexity.