Abstract: According to the present disclosure, a measuring method of liquid mixture purity includes steps as follows. A storage tank is provided, wherein the storage tank is configured for storing a liquid mixture including formic acid and water. A calculating unit is provided, wherein a plurality of formic acid purity values are saved in the calculating unit. A pressure-decreasing and heating step is performed by reducing a pressure of the storage tank and heating the storage tank. A measuring step is performed by measuring in the inner space of the storage tank to obtain a pressure value, and measuring the liquid mixture simultaneously to obtain a temperature value. A calculating step is performed by inputting the pressure value and the temperature value into the calculating unit, wherein the calculating unit outputs one of the formic acid purity values corresponding thereto.

Abstract: Controlling power consumption at an IHS, including receiving electrical power associated with an initial voltage at a first time; determining that the IHS is to enter a low-power state, and in response: adjusting an UVP parameter for the electrical power from a first voltage to a second voltage, the second voltage less than the first voltage, the second voltage based on the low-power state; adjusting an OCP parameter for the electrical power from a first amperage to a second amperage, the second amperage less than the first amperage, the second amperage based on the low-power state; trimming the initial voltage of the electrical power to a trimmed voltage, the trimmed voltage less the initial voltage and greater than the second voltage; adjusting the power state of the IHS to the low-power state; receiving the electrical power having the trimmed voltage at a second time after the first time.

Abstract: Controlling power consumption at an IHS, including receiving electrical power associated with an initial voltage at a first time; determining that the IHS is to enter a low-power state, and in response: adjusting an UVP parameter for the electrical power from a first voltage to a second voltage, the second voltage less than the first voltage, the second voltage based on the low-power state; adjusting an OCP parameter for the electrical power from a first amperage to a second amperage, the second amperage less than the first amperage, the second amperage based on the low-power state; trimming the initial voltage of the electrical power to a trimmed voltage, the trimmed voltage less the initial voltage and greater than the second voltage; adjusting the power state of the IHS to the low-power state; receiving the electrical power having the trimmed voltage at a second time after the first time.

Abstract: A method for increasing power supply voltage in an information handling system in a normal mode with a first peak voltage comprises, in response to receiving a request for a higher peak voltage, an embedded controller (EC) receiving information associated with the application including a request for power at a higher peak voltage, a housekeeping IC communicating a signal to a PWM IC to increase voltage supplied to the information handling system to the higher peak voltage, the PWM IC converting from the PSU to the higher peak voltage and starting a timer with a defined time period. If no additional requests for operating at the higher peak voltage are received before the time period expires, the PWM IC communicates a signal that power will stop being supplied at the higher peak voltage, and the information handling system returns to operating in the normal mode at the first peak voltage.

Abstract: A method for increasing power supply voltage in an information handling system in a normal mode with a first peak voltage comprises, in response to receiving a request for a higher peak voltage, an embedded controller (EC) receiving information associated with the application including a request for power at a higher peak voltage, a housekeeping IC communicating a signal to a PWM IC to increase voltage supplied to the information handling system to the higher peak voltage, the PWM IC converting from the PSU to the higher peak voltage and starting a timer with a defined time period. If no additional requests for operating at the higher peak voltage are received before the time period expires, the PWM IC communicates a signal that power will stop being supplied at the higher peak voltage, and the information handling system returns to operating in the normal mode at the first peak voltage.

Abstract: A planar heating structure is disclosed. The planar heating structure includes a glass substrate layer, a nanometallic transparent conductive layer, and a first passivation layer. The nanometallic transparent conductive layer is disposed on the glass substrate layer and receives a voltage to generate heat energy. The first passivation layer is disposed on the nanometallic transparent conductive layer and completely covers the nanometallic transparent conductive layer.

Abstract: Systems and methods are provided to implement power supply units (PSUs) that are capable of operating on input power having different types of input voltage waveforms, including, but not limited to, pure sinusoidal waveforms, non-pure sinusoidal waveforms, and non-sinusoidal waveforms. Such a PSU may operate to continue supplying DC output power to a system load as long as the PSU is powered by any one of a variety of such different input power types, while at the same time also effectively monitoring for presence of input power provided to the PSU and shutting down the PSU in event of absence or termination of the input power to the PSU. Such a PSU may also automatically identify and adapt to changes between different types of input power while at the same time continuing to supply DC output power to a system load in an uninterrupted manner for as long as some type of input power is being provided to the PSU.

Abstract: Systems and methods are provided to implement power supply units (PSUs) that are capable of operating on input power having different types of input voltage waveforms, including, but not limited to, pure sinusoidal waveforms, non-pure sinusoidal waveforms, and non-sinusoidal waveforms. Such a PSU may operate to continue supplying DC output power to a system load as long as the PSU is powered by any one of a variety of such different input power types, while at the same time also effectively monitoring for presence of input power provided to the PSU and shutting down the PSU in event of absence or termination of the input power to the PSU. Such a PSU may also automatically identify and adapt to changes between different types of input power while at the same time continuing to supply DC output power to a system load in an uninterrupted manner for as long as some type of input power is being provided to the PSU.

Abstract: A conductive structure includes a first wire, a second wire, and a conductive pillar. The second wire is disposed over the first wire and intersected with the first wire. The conductive pillar is disposed between the first wire and the second wire. A bottom surface area of the conductive pillar is greater than an area at which the first wire overlaps the conductive pillar.

Abstract: A conductive structure includes a first wire, a second wire, and a conductive pillar. The second wire is disposed over the first wire and intersected with the first wire. The conductive pillar is disposed between the first wire and the second wire. A bottom surface area of the conductive pillar is greater than an area at which the first wire overlaps the conductive pillar.

Abstract: A planar heating structure is disclosed. The planar heating structure includes a glass substrate layer, a nanometallic transparent conductive layer, and a first passivation layer. The nanometallic transparent conductive layer is disposed on the glass substrate layer and receives a voltage to generate heat energy. The first passivation layer is disposed on the nanometallic transparent conductive layer and completely covers the nanometallic transparent conductive layer.

Abstract: A system and method of operating an a power supply unit with a light load efficiency control system comprising a power regulator circuit for receiving an alternating current (AC) input voltage from within a range of accommodated AC input voltages and including a power factor correction (PFC) circuit and an LLC resonator circuit having a bulk capacitance voltage level and operable to receive the input AC voltage in the power supply unit and where the power supply unit generates a direct current (DC) output voltage for use by a load.

Abstract: A semiconductor device includes a fin-like structure. The fin-like structure includes a bottom layer formed of silicon and at least a top layer formed of germanium. The semiconductor device further includes a gate stack feature overlaying a central upper portion of the fin-like structure, wherein the gate stack is in contact with a top surface and sidewalls of the top layer, and at least part of sidewalls of the bottom layer.

Abstract: A system and method of operating an a power supply unit with a light load efficiency control system comprising a power regulator circuit for receiving an alternating current (AC) input voltage from within a range of accommodated AC input voltages and including a power factor correction (PFC) circuit and an LLC resonator circuit having a bulk capacitance voltage level and operable to receive the input AC voltage in the power supply unit and where the power supply unit generates a direct current (DC) output voltage for use by a load.

Abstract: Systems and methods are provided that may be implemented for overvoltage protection of bulk capacitors employed in power factor correction (PFC) circuitry components of switched mode power supply units (PSUs) using one or more inductive overvoltage feedback protection paths (OVPs) to monitor a voltage indicative of a PFC bulk capacitor by sensing the real time voltage at one or both of the primary and/or secondary side windings of a PSU transformer, and/or using an auxiliary windings of a PSU transformer.

Abstract: The present invention provides a microfluidic chip for culturing microorganism and a method of operating the same. The microfluidic chip includes a first input unit, a second input unit, a connection unit connected to the first and second input units, a plurality of control valves, and a ring-shaped storage structure connected to the connection unit and having first and second growth chambers that store a microbial solution. The first and second input units provide first and second solutions, respectively. The first solution is transferred into the first or second growth chamber through the connection unit to treat and discharge a portion of the microbial solution. The second solution is transferred into the first or second growth chamber to discharge the first solution. The control valves are actuated to mix the second solution and remainder of the microbial solution in the ring-shaped storage structure.

Abstract: Systems and methods are provided that may be implemented for overvoltage protection of bulk capacitors employed in power factor correction (PFC) circuitry components of switched mode power supply units (PSUs) using one or more inductive overvoltage feedback protection paths (OVPs) to monitor a voltage indicative of a PFC bulk capacitor by sensing the real time voltage at one or both of the primary and/or secondary side windings of a PSU transformer, and/or using an auxiliary windings of a PSU transformer.

Abstract: Methods for forming a film stack suitable for transistor fabrication using a low temperature plasma enhanced chemical vapor deposition (PECVD) process are provided. In one embodiment, the method includes providing a substrate in a PECVD chamber, depositing a dual layer SiNx film on the substrate, depositing a dual layer amorphous silicon film on the SiNx film, and depositing a n-doped silicon film on the dual layer amorphous silicon film. The aforementioned films are deposited at a temperature less than about 300 degrees Celsius in the same PECVD chamber.

Abstract: A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich silicon nitride layer. An active layer is formed, which may also be a bilayer, the first active layer deposited at a low rate and the second at a high rate. The thin film transistors described herein have superior mobility and stability under stress.

Abstract: The present invention relates to a chip resistor having low resistance and a method for manufacturing the same. The chip resistor includes a substrate, a resistive layer, a pair of conducting layers and at least one protective layer. The substrate has a first surface. The resistive layer is disposed on the first surface of the substrate. The conducting layers are disposed adjacent to the first surface of the substrate. The at least one protective layer is disposed on the resistive layer or the conducting layers. As a result, the resistive layer has a precise pattern, and the duration of sputtering is reduced, thereby improving yield rate and efficiency while reducing manufacturing cost.