Abstract: A fan includes a hub, a plurality of blades, and a heat dissipation module. The blades surround the hub. The heat dissipation module includes a plurality of fins. The fins are disposed around the hub with respect to the blades. The end face of each fin facing the blades includes a noise reduction structure. The noise reduction structure is an inclined plane.

Abstract: A touch panel capable of being simply manufactured includes a foldable substrate, a plurality of touch driving electrodes on the substrate, and a plurality of touch sensing electrodes on the substrate. The substrate includes two laminated layers achieved by folding. The touch driving electrodes are on one of the two laminated layers and the touch sensing electrodes are on the other of the two laminated layers. The touch driving electrodes and the touch sensing electrodes are formed by a same conductive layer on a surface of the substrate.

Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy.

Abstract: A multi-processor system includes multiple processors arranged in multiple clusters. Different clusters have different power and performance characteristics. The system includes a task scheduler to schedule tasks to the processors. The task scheduler, in response to detection of a scheduling event trigger, is operative to identify a scheduling objective between a first objective of energy optimization and a second objective of load balance. The scheduling objective is identified based on at least respective operating frequencies and loading of all processors in a highest-capacity cluster of the multiple clusters. According to the identified scheduling objective, the task scheduler schedules a given task to a processor selected among the processors in the multiple clusters.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: Disclosed herein is a mobile plastic recycling system mounted in a vehicle. The system is configured to process a plastic article and make it into thermoplastic items. The mobile plastic recycling system includes a plastic recycling apparatus and a power supply apparatus that are electrically coupled with each other; the system also includes a vehicle configured to carry and transport the power supply apparatus and plastic recycling apparatus.

Abstract: A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

Abstract: Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.

Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

Abstract: A manufacturing method of 3D glass includes steps of precutting and drilling a 2D glass substrate by means of perfect laser cleaving and using a complex molding equipment to process and mold a 3D glass object with 3D curved structure. By means of the manufacturing method of 3D glass, the structural strength of the 3D glass object is enhanced. In addition, a 3D glass product with special surface texture or morphology can be produced. Also, the defective ratio in the manufacturing process can be lowered.

Abstract: A multi-core processor system and method are provided. The multi-core processor system includes a plurality of processor cores and a task scheduler. The processor cores perform a plurality of tasks, wherein each of the tasks is in a respective one of a plurality of scheduling classes. The task scheduler obtains first task assignment information about tasks which are in a first scheduling class from the scheduling classes and assigned to the processor cores, obtains second task assignment information about tasks in one or more other scheduling classes and assigned to the processor cores, and refers to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores. Prior to the assigning the runnable task, the runnable task has been assigned to one of the processor cores.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

Abstract: Provided is a polyimide insulation coating, which is prepared by reacting a diacid anhydride compound represented by Formula (I) with a diamine compound represented by Formula (II). By adopting the specific diacid anhydride compound and the specific diamine compound, the synthesized polyimide insulation coating can have a dielectric constant less than 3. Accordingly, the enameled wire having an insulation layer formed from the polyimide insulation coating would not readily produce partial discharge, thereby avoiding the penetrating short-circuit and the damage to the motor.

Abstract: A task scheduling method is applied to a heterogeneous multi-core processor system. The heterogeneous multi-core processor system has at least one first processor core and at least one second processor core. The task scheduling method includes: referring to task priorities of tasks of the heterogeneous processor cores to identify at least one first task of the tasks that belongs to a first priority task group, wherein each first task belonging to the first priority task group has a task priority not lower than task priorities of other tasks not belonging to the first priority task group; and dispatching at least one of the at least one first task to at least one run queue of at least one of the at least one first processor core.

Abstract: A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

Abstract: A CPU control method for controlling a first CPU and a second CPU The method comprises: (a) applying the first CPU to execute a first group of codes comprising at least one code if the first CPU is operating to perform a first function; and (c) applying the second CPU to execute a second group of codes comprising at least one code if the second CPU is operating to perform the first function. The first group of codes is optimized for the first CPU, the second group of codes is optimized for the second CPU and the first group of codes comprises at least one code different from the code for the second group of codes.

Abstract: A fan includes a hub, a plurality of blades, and a heat dissipation module. The blades surround the hub. The heat dissipation module includes a plurality of fins. The fins are disposed around the hub with respect to the blades. The end face of each fin facing the blades includes a noise reduction structure. The noise reduction structure is an inclined plane.