Abstract: A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

Abstract: An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Abstract: A display panel includes a control circuit and a pixel structure. The control circuit selectively provides a data signal or a first reference voltage signal. The pixel structure includes a capacitor, a first, a second and a third switch unit. For the first switch unit, a first and a second terminal are coupled to two the capacitor in series, and a control terminal receives a control signal. For the second switch unit, a first terminal is coupled to the second terminal of the first switch unit, and the control terminal receives a first scan signal. For the third switch unit, a first terminal receives the data or first reference voltage signal, a second terminal is coupled to the second terminal of the second switch unit and a light emitting element, and the control terminal is coupled to the second terminal of the first switch unit.

Abstract: An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Abstract: A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.

Abstract: A process for treating halide contaminated waste includes bringing the contaminated waste into contact with a reductone in an aqueous solution to obtain a mixture having a pH value, and adjusting the pH value to permit dissociation of two hydrogen ions from an enediol group of the reductone and to permit subsequent reaction of the reductone with an electrophilic site of halide contained in the contaminated waste. Halide can thus be removed.

Abstract: An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.

Abstract: A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.

Abstract: A display panel includes a control circuit and a pixel structure. The control circuit selectively provides a data signal or a first reference voltage signal. The pixel structure includes a capacitor, a first, a second and a third switch unit. For the first switch unit, a first and a second terminal are coupled to two the capacitor in series, and a control terminal receives a control signal. For the second switch unit, a first terminal is coupled to the second terminal of the first switch unit, and the control terminal receives a first scan signal. For the third switch unit, a first terminal receives the data or first reference voltage signal, a second terminal is coupled to the second terminal of the second switch unit and a light emitting element, and the control terminal is coupled to the second terminal of the first switch unit.

Abstract: An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.

Abstract: A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

Abstract: A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

Abstract: A process for treating halide contaminated waste includes bringing the contaminated waste into contact with a reductone in an aqueous solution to obtain a mixture having a pH value, and adjusting the pH value to permit dissociation of two hydrogen ions from an enediol group of the reductone and to permit subsequent reaction of the reductone with an electrophilic site of halide contained in the contaminated waste. Halide can thus be removed.

Abstract: A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Abstract: A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

Abstract: A display panel is provided. A substrate includes a non-display area and a display area including a center area, a first area, and a second area. First data lines are disposed in the first area and electrically connected to the first source driving circuit. Second data lines are disposed in the second area and electrically connected to the second source driving circuit. At least one first repairing line is electrically connected to the first source driving circuit, passes through the center area of the display area and overlaps with the first data lines, wherein the first repairing line is electrically insulated from the first data lines. At least one second repairing line is electrically connected to the second source driving circuit, passes through the center area of the display area and overlaps with the second data lines, wherein the second repairing line is electrically insulated from the second data lines.

Abstract: A method for use in a display panel is disclosed. The method includes providing M bus lines in the bus area for receiving a plurality of clock signals, M being a positive integer greater than 3; providing a plurality of signal lines to separately provide the clock signals from the M bus line to the circuit area, the circuit area configured to provide the plurality of sequential gate line signals in response to the clock signals, the plurality of signal lines including a plurality of adjacent signal-line pairs, each adjacent signal-line pair having a resistance difference, said signal lines including a maximum resistance value and a minimum resistance value, and wherein the M bus lines are arranged such that the resistance difference in any one of the adjacent signal-line pairs is smaller than a value difference between the maximum resistance value and the minimum resistance value.

Abstract: A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.