Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Abstract: A coplanar transformer with a capacitor that has the advantage of high space utilization is provided. The coplanar transformer comprises a primary coil and a secondary coil constructed by many conductor segments in a first metal layer and connectors in a second metal layer. The upper plate and lower plate of the capacitor are electrically coupled with the two terminals of the primary coil separately. The upper plate comprises the extended plate from the connected terminal toward the other terminal and the connected conductor segment in the first metal layer, and the lower plate locates in the second metal layer corresponding to the upper plate.

Abstract: A coplanar transformer with a capacitor that has the advantage of high space utilization is provided. The coplanar transformer comprises a primary coil and a secondary coil constructed by many conductor segments in a first metal layer and connectors in a second metal layer. The upper plate and lower plate of the capacitor are electrically coupled with the two terminals of the primary coil separately. The upper plate comprises the extended plate from the connected terminal toward the other terminal and the connected conductor segment in the first metal layer, and the lower plate locates in the second metal layer corresponding to the upper plate.

Abstract: An integrated circuit with electrostatic discharge (ESD) protection is disclosed. The integrated circuit with electrostatic discharge protection comprises an inductor and a capacitor which can cancel the reactance induced by electrostatic discharge protection elements at an operating radio frequency. By choosing the combination of ESD protection elements, the inductor and the capacitor with proper equivalent reactance values, the mismatch caused by ESD protection elements can be eliminated at an operating radio frequency.