Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have, a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion d having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A lead frame and a semiconductor package with the lead frame are provided. The lead frame includes a die pad for mounting at least one semiconductor chip thereon; at least one grounding portion protruded from the die pad; and a plurality of leads. The grounding portion has a grounding surface and an opposing bottom surface, wherein the thickness of the grounding portion is smaller than that of the die pad, and a ground pad is formed on the grounding surface for connecting at least one grounding wire to the chip for transmitting ground signals. A plurality of bonding wires are connected from the chip to the leads such that the chip can be electrically connected to an external device via the bonding wires and leads. By the above arrangement, the grounding wire can be prevented from breakage by thermal stress in a high-temperature process, and the production yield is improved.

Abstract: A lead frame and a semiconductor package with the lead frame are provided. The lead frame includes a die pad for mounting at least one semiconductor chip thereon; at least one grounding portion protruded from the die pad; and a plurality of leads. The grounding portion has a grounding surface and an opposing bottom surface, wherein the thickness of the grounding portion is smaller than that of the die pad, and a ground pad is formed on the grounding surface for connecting at least one grounding wire to the chip for transmitting ground signals. A plurality of bonding wires are connected from the chip to the leads such that the chip can be electrically connected to an external device via the bonding wires and leads. By the above arrangement, the grounding wire can be prevented from breakage by thermal stress in a high-temperature process, and the production yield is improved.

Abstract: A semiconductor package for chip with testing contact pad includes a chip, a plurality of leads, at least a flow-conducting plate, and a molding compound. The chip has an active surface provided with a plurality of functional contact pads and at least a testing contact pad. The leads are bonded onto the active surface of the chip and respectively connected to the functional contact pads through a plurality of functional wires. The flow-conducting plate is connected to the testing contact pad through at least a testing wire. The molding compound encapsulates the chip, the leads, the flow-conducting plate, the functional contact pads, and the testing contact pads.

Abstract: A multi-die IC package structure and a method of manufacturing this multi-die IC package structure are proposed. This multi-die IC package structure is constructed on a lead frame including an inner-lead part having a plurality of inner leads surrounding a cavity in the center thereof, without the forming of a die pad. Next, a stacked multi-die structure is mounted on the inner-lead part of the lead frame, which is formed in such a manner the undermost semiconductor die has its non-circuit surface insulatively attached to the inner-lead part of the lead frame and its circuit surface insulatively attached to the overlying one, and also in such a manner that each of the semiconductor dies other than the undermost one has its non-circuit surface insulatively attached to the circuit surface of the underlying one. By the proposed method, the overall packaging process is significantly less complex than the prior art, thus allowing the manufacture process more cost-effective to carry out.

Abstract: A disturbing plate structure having at least one down set, applicable in a lead frame-type package in a semiconductor. The disturbing plate has at least a lead frame, a die, a glue layer, a plurality of disturbing plates, a top mold compound, and a bottom mold compound. The lead frame has a plurality of leads. Two disturbing plates are located on two sides of the die. A space is formed by bending a first bent portion and a second bent portion of the disturbing plate down. Finally, the lead frame is encapsulated with a mold compound. By adjusting the size of the space formed by the first bent portion and the second bent portion, the top mold compound section has substantially the same volume as the bottom mold compound section to finish the packaging and forming.

Abstract: A semiconductor package for chip with testing contact pad comprises a chip, a plurality of leads, at least a flow-conducting plate, and a molding compound. The chip has an active surface provided with a plurality of functional contact pads and at least a testing contact pad. The leads are bonded onto the active surface of the chip and respectively connected to the functional contact pads through a plurality of functional wires. The flow-conducting plate is connected to the testing contact pad through at least a testing wire. The molding compound encapsulates the chip, the leads, the flow-conducting plate, the functional contact pads, and the testing contact pads.