Patents by Inventor Ya-Yun Cheng

Ya-Yun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150016080
    Abstract: A method for manufacturing an embedded package comprises the steps of: coupling at least one first embedded body including at least one connection port with a first circuit substrate and packaging the first embedded body and the first circuit substrate to form a package; and exposing the connection port of the package on an outer side of the package for other electronic carriers to couple with. The invention can overcome the disadvantage of the conventional System in Package manufacturing process which integrally packages multiple ICs in a same package to result in discard of the entire package because of failure of a single IC. The method of the invention makes assembly simpler, expansion, test and replacement of IC components easier, and also can reduce manufacturing time and accumulated heat, lower the cost and improve yield rate.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: Chen Hsuan Lung, Chien Hsien Lu, Ya Yun Cheng, Kuo Hua Lin
  • Publication number: 20140349458
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Tzer-Min Shen, Ya-Yun Cheng
  • Patent number: 8884640
    Abstract: An integrated high-speed probe system is provided. The integrated high-speed probe system includes a circuit substrate for transmitting low-frequency testing signals from a tester through a first probe of the probe assembly to a DUT, and a high-speed substrate for transmitting high-frequency testing signals from the tester to the DUT. The high-speed substrate extends from the upper surface of the circuit substrate in the testing area to the lower surface of the circuit substrate in the probe area for being adjacent to the probe assembly and electrically connecting the second probe. In this way, the tester can transmit testing signals of different frequencies through the integrated high-speed probe system.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 11, 2014
    Assignee: MPI Corporation
    Inventors: Chun-Chi Wang, Chia-Tai Chang, Ya-Yun Cheng, Wei-Cheng Ku, Chao-Ping Hsieh
  • Patent number: 8866235
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Ya-Yun Cheng, Tzer-Min Shen
  • Patent number: 8788185
    Abstract: A method and system for estimating traffic information by using integration of location update events and call events uses a sample capturing and analyzing device to associate location area update (LAU) and call sample data of a plurality of mobile users. The sample data at least includes at least one LAU event of at least one mobile user of the plurality of mobile users, and call arrival (CA) or call completion (CC) events of at least one call. Based on the sample data, a computation device is used to determine the location information and time information of the at least one LAU event and the CA or CC event of the at least one call, and estimate traffic information of one or more designated roads according to the location information and time information.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: July 22, 2014
    Assignees: Industrial Technology Research Institute, Chunghwa Telecom Co., Ltd.
    Inventors: Sheng-Ying Yen, Chih-Yen Huang, Ya-Yun Cheng, Chien-Hsiang Chen, Chung-Yung Chia
  • Publication number: 20140131812
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Ya-Yun Cheng, Tzer-Min Shen
  • Publication number: 20140011484
    Abstract: A method and system for estimating traffic information by using integration of location update events and call events uses a sample capturing and analyzing device to associate location area update (LAU) and call sample data of a plurality of mobile users. The sample data at least includes at least one LAU event of at least one mobile user of the plurality of mobile users, and call arrival (CA) or call completion (CC) events of at least one call. Based on the sample data, a computation device is used to determine the location information and time information of the at least one LAU event and the CA or CC event of the at least one call, and estimate traffic information of one or more designated roads according to the location information and time information.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 9, 2014
    Inventors: Sheng-Ying YEN, Chih-Yen Huang, Ya-Yun Cheng, Chien-Hsiang Chen, Chung-Yung Chia
  • Patent number: 8619431
    Abstract: The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 31, 2013
    Assignee: ADL Engineering Inc.
    Inventors: Nan-Chun Lin, Ya-Yun Cheng
  • Publication number: 20130263599
    Abstract: A thermal magnetic engine and a thermal magnetic engine system are disclosed. The thermal magnetic engine includes a fixed element, a rotation element, working fluid and a fin structure. The rotation element includes a working material. The rotation element rotates relative to the fixed element. The working fluid flows through the rotation element and forms a temperature difference on the working material. The fin structure is disposed on the rotation element. The rotation element rotates along a rotating direction due to the temperature difference on the working material and/or due to the flowing of the first working fluid through the fin structure.
    Type: Application
    Filed: September 14, 2012
    Publication date: October 10, 2013
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Chung-Jung KUO, Tze-Chern MAO, Min-Tsz LIN, Chieh-Cheng LIU, Mao-Jen HSU, Ya-Yun CHENG, Cheng-Yen SHIH
  • Publication number: 20130044288
    Abstract: An eyeglass structure mainly has a frame. Two extension segments are provided respectively at both sides of the eyeglass frame and the extension segments combine with connectors for pivotal connection with eyeglass temples. Each extension segment has an elastic portion which is connected with one end of a link member. The other end of each link member is in hooking engagement with an eyeglass temple. When the temples are unfolded to open, the elastic portions are deformed by the press from the link members so as to fix the unfolding state of the eyeglass temples. The eyeglass temples can be folded with only slight push by the elastic recovery force of the elastic portions.
    Type: Application
    Filed: December 1, 2011
    Publication date: February 21, 2013
    Applicant: EAKAU INTERNATIONAL OPTICAL-ELECTRONIC CO., LTD.
    Inventor: YA-YUN CHENG
  • Patent number: 8371866
    Abstract: The present invention discloses a card connector which comprises an insulating body, a plurality of conductive terminals, an ejection mechanism, a tray, and a metal shell. The insulating body has a substrate. One side of the substrate is perforated to form a guide groove of which a bottom surface is a cylindrical surface. The ejection mechanism comprises a pushing shaft, a plurality of balls, a sliding bulk, and a pressing element. The pushing shaft, the plural balls, and the sliding bulk are slidably disposed in the guide groove. The plural balls are located between the pushing shaft and the sliding bulk and can be rolled sequentially. By the design of the ejection mechanism constructed by the pushing shaft, the plural balls, the sliding bulk, and the pressing element, the present invention has an advantage of making the card connector to be of a small size.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: February 12, 2013
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventors: Yu-hung Su, Ya-yun Cheng
  • Publication number: 20120274347
    Abstract: An integrated high-speed probe system is provided. The integrated high-speed probe system includes a circuit substrate for transmitting low-frequency testing signals from a tester through a first probe of the probe assembly to a DUT, and a high-speed substrate for transmitting high-frequency testing signals from the tester to the DUT. The high-speed substrate extends from the upper surface of the circuit substrate in the testing area to the lower surface of the circuit substrate in the probe area for being adjacent to the probe assembly and electrically connecting the second probe. In this way, the tester can transmit testing signals of different frequencies through the integrated high-speed probe system.
    Type: Application
    Filed: April 18, 2012
    Publication date: November 1, 2012
    Inventors: Chun-Chi Wang, Chia-Tai Chang, Ya-Yun Cheng, Wei-Cheng Ku, Chao-Ping Hsieh
  • Publication number: 20120188727
    Abstract: The present invention discloses a package module with EMI shielding and the method thereof. The package module has a substrate or a PCB with at least one ground pad. A variety of electronic components are mounted on the substrate. The dielectric layer overlays a selected area which covers some electronic components and ground pads. Openings are formed within the dielectric layer and above ground pads. The shielding layer with at least two metal layers covers the dielectric layer and is electrically coupled, via the openings, to the ground pad. In general, there is a protection layer to encapsulate the entire substrate. The package module of the present invention not only achieves the requirement of miniature packaging but also reduces EMI caused by high speed electronic devices.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: ADL Engineering Inc.
    Inventors: Nan-Chun LIN, Ya-Yun Cheng, Jing-Hua Cheng, Kuang-San Liu
  • Publication number: 20120161315
    Abstract: The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Nan-Chun Lin, Ya-Yun Cheng
  • Patent number: 6570263
    Abstract: The present invention provides a design structure of an plated wire of a fiducial mark for a die-dicing package. In the present structure, a cutting line is positioned between each two adjacent ball grid array (BGA) chips. There is configured a solder mask opening at the edge connecting region of the cutting lines. A fiducial mark is positioned in the opening of each BGA chip, wherein the fiducial mark is close to the cutting line and positioned a plated wire therein to pull from the fiducial mark to out the opening and to connect to the plated wire of the cutting line. So as all the plated wires utilizing the coverage of the solder mask can be entirely cut without the pulling problem from the cutter. The present invention provides a new design structure of the plated wire to overcome the burr effect of prior die dicing so as to enhance the product efficiency and decrease the manufacturing cost.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: May 27, 2003
    Assignee: Vate Technology Co., Ltd.
    Inventors: Kai-Chiang Wu, Yi-Liang Peng, Ya-Yun Cheng