Abstract: A short-circuit-resistant relay includes a fixed base, a contact lead-out end, a push rod assembly, a first and a second magnetically guiding sheet. Provided are at least two contact lead-out ends providing with stationary contact, both ends of the movable spring sheet are provided with movable contacts, the first magnetically guiding sheet is movably provided, along a direction in parallel to the movement of the movable spring sheet, on a side of the movable spring sheet facing the stationary contact, and the second magnetically guiding sheet is provided on a side of the movable spring sheet distal to the stationary contact, in which the first and second magnetically guiding sheets are capable of forming a magnetic loop, and the first magnetically guiding sheet moves in a direction facing the second magnetically guiding sheet and in parallel to the movement of the movable spring sheet within a preset travel.

Abstract: An electrocardio-signal collection system and method, and preparation method of an electrocardio-signal collection system is provided. The system includes: a collection unit configured to collect an analog electrocardio-signal of a human body, where the collection unit includes a flexible device and 10 conductive electrodes (2), and the conductive electrodes (2) are printed on the flexible device; a control unit connected to the conductive electrodes (2) and configured to process and output the analog electrocardio-signal; and a display unit connected to the control unit and configured to receive an output signal from the control unit and display the output signal. The collection unit in the conductive electrodes (2) printed on the flexible device is used as a collection carrier for an electrocardio-signal, and all the conductive electrodes (2) are put in place at once, thereby improving the convenience of electrocardio-signal collection.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.

Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Abstract: A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.