Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a word line, and at least two dielectric layers. The word line is arranged in the substrate; the at least two dielectric layers are located between the word line and the substrate and have different dielectric constants.

Abstract: A semiconductor structure includes a substrate and a word line (WL) structure. The WL structure includes: a work function stacking structure located in the substrate, where the work function stacking structure includes multiple sequentially and alternately stacked first work function layers and second work function layers, and a work function of the first work function layer is greater than a work function of the second work function layer; a WL conductive layer located in the substrate, and located on an upper surface of the work function stacking structure; and a gate oxide layer located between the work function stacking structure and the substrate as well as between the WL conductive layer and the substrate.

Abstract: The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.

Abstract: An industrialization method for comprehensive utilization of Stevia rebaudiana. The major improvement is in that the Stevia rebaudiana is extracted by using a high-concentration alcohol solution, then the extracted solution is purified by using an organic solvent, and the pH of the extracted solution is adjusted to be alkaline according to the acidic characteristic of chlorogenic acid to enable the chlorogenic acid to be formed into a salt and have an increased polarity so as to achieve effective separation of the chlorogenic acid and a glucoside component in an adsorption process. The method allows the high-quality stevioside and chlorogenic acid to be obtained, significantly improves the comprehensive utilization rate of Stevia rebaudiana, reduces the waste of natural Stevia rebaudiana resources, reduces the resource consumption in a production process, reduces waste discharge, and is a high-benefit green production process.

Abstract: Embodiments of the present disclosure relate to the field of semiconductor structures, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a plurality of first conductive structures, located on a surface of the base and distributed at intervals along a first direction; a plurality of second conductive structures, located on the surface of the base, and the plurality of second conductive structures and the plurality of first conductive structures being arranged alternately; and a plurality of support structures, located on the surface of the base and a given one of the plurality of support structures being located between a given one of the plurality of first conductive structures and a given one of the plurality of second conductive structures.

Abstract: A semiconductor structure and a manufacturing method therefor are provided. The semiconductor structure includes: a substrate; a plurality of connection pads disposed on a surface of the substrate; and a plurality of electrode pillars, disposed on the substrate and connected to the plurality of connection pads in a one-to-one correspondence. Each electrode pillar includes a first conductor layer and a second conductor layer that are alternately distributed in a direction perpendicular to the substrate. A material of the first conductor layer is different from a material of the second conductor layer. A side surface of the first conductor layer is recessed inward relative to a side surface of the second conductor layer.

Abstract: A method for forming a memory includes: forming a bit line structure and a capacitor contact layer, where the bit line structure includes a bit line, a bit line cap layer and a bit line isolation layer, and the capacitor contact layer covers part of a side wall of the bit line isolation layer; forming a stop layer covering the side wall of the bit line isolation layer; forming a capacitor landing layer covering a top surface of the capacitor contact layer; and etching the bit line isolation layer by using the stop layer as an etch stop layer to form an air gap in the bit line isolation layer. Probability of occurrence of a short circuit between the capacitor landing layer and a bit line is reduced.

Abstract: Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

Abstract: The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.

Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided. The semiconductor structure includes: a substrate; an active region, located in the substrate; and gate trenches, intersected with the active region and dividing the active region into at least one source region and two drain regions, the source region including a first doped region and a first extended doped region below the first doped region.

Abstract: A method for preparing a semiconductor structure and the semiconductor structure are provided. The method for preparing the semiconductor structure comprises: providing a semiconductor substrate and forming a conductive layer on the semiconductor substrate; forming a first protective layer on a surface of the conductive layer; performing a passivation treatment on the first protective layer to enable the first protective layer to form a passivation layer, wherein the passivation layer comprises a multilayer thin film structure and ion concentrations of the multilayer thin film structure are not the same; forming an insulation layer on the passivation layer; and sequentially forming a barrier layer and a second protective layer on the insulation layer.

Abstract: A semiconductor structure includes: a semiconductor substrate; interlayer dielectric layers located above the semiconductor substrate and at least two metal interconnection layers located in the interlayer dielectric layers; a laser fuse located in any metal interconnection layer above the bottom metal interconnection layer and metal islands located in the metal interconnection layers below the laser fuse, the metal islands in different metal interconnection layers being connected through conductive contact holes to form two conductive paths, the laser fuse connecting the two conductive paths in series through the conductive contact holes; and, an alignment mark located in the same metal interconnection layer as the laser fuse, the alignment mark being used as a mark for laser alignment during fusing the laser fuse.

Abstract: An industrialization method for comprehensive utilization of Stevia rebaudiana. The major improvement is in that the Stevia rebaudiana is extracted by using a high-concentration alcohol solution, then the extracted solution is purified by using an organic solvent, and the pH of the extracted solution is adjusted to be alkaline according to the acidic characteristic of chlorogenic acid to enable the chlorogenic acid to be formed into a salt and have an increased polarity so as to achieve effective separation of the chlorogenic acid and a glucoside component in an adsorption process. The method allows the high-quality stevioside and chlorogenic acid to be obtained, significantly improves the comprehensive utilization rate of Stevia rebaudiana, reduces the waste of natural Stevia rebaudiana resources, reduces the resource consumption in a production process, reduces waste discharge, and is a high-benefit green production process.