Patents by Inventor Yacine Felk

Yacine Felk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190212985
    Abstract: Some embodiments provide methods and apparatus for quantum random number generation based on a single bit or multi bit Quanta Image Sensor (QIS) providing single-photon counting over a time interval for each of an array of pixels of the QIS, wherein random number data is generated based on the number of photons counted over the time interval for each of the pixels.
    Type: Application
    Filed: May 5, 2017
    Publication date: July 11, 2019
    Applicants: ID QUANTIQUE SA, TRUSTEES OF DARTMOUTH COLLEGE
    Inventors: Emna Amri, Yacine Felk, Damien Stucki, Jiaju Ma, Eric R. Fossum
  • Patent number: 8828797
    Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics SA
    Inventors: Perceval Coudrain, Yacine Felk, Patrick Lamontagne
  • Patent number: 8766381
    Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 1, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Fabrice Casset, Lionel Cadix, Perceval Coudrain, Alexis Farcy, Laurent-Luc Chapelon, Yacine Felk, Pascal Ancey
  • Patent number: 8704363
    Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: April 22, 2014
    Assignee: STMicroelectronics S.A.
    Inventors: Yacine Felk, Alexis Farcy
  • Publication number: 20120074527
    Abstract: The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 29, 2012
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Fabrice Casset, Lionel Cadix, Perceval Coudrain, Alexis Farcy, Laúrent-Lüc Chapelon, Yacine Felk, Pascal Ancey
  • Publication number: 20120052629
    Abstract: A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Perceval Coudrain, Yacine Felk, Patrick Lamontagne
  • Publication number: 20110095437
    Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 28, 2011
    Applicant: STMicroelectronics S.A.
    Inventors: Yacine Felk, Alexis Farcy
  • Publication number: 20110086468
    Abstract: A method for assembling a first semiconductor chip provided with pads on a second semiconductor chip or wafer provided with pads, comprising covering the chip(s) with a dielectric, superposing the two chips, the pads being arranged substantially opposite to each other, and applying a voltage difference between the pads of the first and second chips to cause a breakdown of the dielectric and a diffusion of the conductor forming the pads into the broken down areas, whereby a conductive path forms between the opposite pads.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 14, 2011
    Inventors: Yacine Felk, Hamed Chaabouni, Alexis Farcy