Abstract: A digital processing system comprises an input configured for receiving data in block exponent integer format, wherein each block comprises a plurality of data values sharing a single exponent. The plurality of data values has a common data bit width, and the exponent has an exponent bit width. An arithmetic processor performs arithmetic operations on the input data to produce output data in block exponent integer format. The arithmetic processor comprises a format optimizer for reducing at least one of the data bit width and the exponent bit width prior to performing arithmetic operations. The bit width is reduced to improve system power efficiency while meeting a predetermined target system performance.