Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: A method that may be performed by a data storage device includes configuring the data storage device to use a first scheduling scheme and, in response to detecting a trigger event, configuring the data storage device to use a second scheduling scheme. One of the first scheduling scheme and the second scheduling scheme is used to schedule performance of memory operations having the same operation type at a plurality of dies of a memory of the data storage device. The other of the first scheduling scheme and the second scheduling scheme is used to schedule memory operations opportunistically.

Abstract: A data retention operation is performed in a non-volatile memory in response to detection of a triggering event. The data retention operation includes updating a value of a write parameter of the non-volatile memory and storing into the non-volatile memory at least one copy of contents of a boot portion of the non-volatile memory using the updated value of the write parameter. The updated value of the write parameter increases retention of stored data during extended periods of inactivity at the non-volatile memory.

Abstract: Techniques are presented to operate a greater number of dice in parallel while not exceeding peak current limits. The device can arbitrate between multiple dice and, when needed, suspend operations on one or more dice in a way to average the chance of performance penalty so that all chips will proceed with write at an equal probability. In other aspects, the suspension of operations can be weighted based on factors such as the relative speed of the different dice or differing loads.

Abstract: A device includes a first leg including a first connector. The first connector includes multiple electrical contacts. The device includes a second leg substantially parallel to the first leg and configured with a connector, a set of conductors, or both. The device includes a transverse portion connected to the first leg and to the second leg. Together, the transverse portion and the first and second legs form a substantially rigid or semi-rigid body. The transverse portion includes multiple conductors electrically coupling respective connectors on the first and second legs.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A data storage device includes a memory and a controller coupled to the non-volatile memory. The controller is coupled to a communication interface that is configured to enable communication with a host device. The controller is configured to send a signal via a first connection of the communication interface and to send a corresponding clock signal via a second connection of the communication interface. The signal is compliant with a communication protocol that specifies that the first connection of the communication interface carries the signal while the second connection of the communication interface carries the clock signal. The first connection is testable to measure the signal to generate data indicating transitions of the signal. The data excludes measurements of the clock signal. The data is analyzable to detect an indication defined by the communication protocol and to determine an estimated bit sequence of the signal.

Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.

Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.

Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.

Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.

Abstract: A method and system for enhancing efficiency in power failure handling in flash memory devices is disclosed. The method includes the controller of a storage device receiving a page of data, selecting a block having a desired back-up cost and copying previously stored data in the selected block to a back-up block prior to writing the received page to the selected block based on a category of the previously stored data. The system includes non-volatile memory having a plurality of operative blocks, at least one spare block and a controller. The controller is configured to receive a page of data, select an operative block in the memory having a desired back-up cost, and copy previously stored data in the selected block to a spare block based on a category of the previously stored data prior to writing the received page to the selected block.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: Circuitry and method for detecting occurrence of a reflow process to an embedded storage device are disclosed. A temperature sensing device includes a resistor, a temperature sensor, and a comparator. The first terminal of the resistor is coupled to a voltage source, and the second terminal of the resistor is coupled to both the first terminal of the temperature sensor and the first input of the comparator. The second terminal of the temperature sensor is grounded and the second input of the comparator is coupled to a reference voltage. The resistance state of the temperature sensor changes from a first resistance state to a second resistance state when the temperature surrounding the temperature sensor reaches a threshold. The comparator generates an output based on the resistance changes of the temperature sensor. The generated output may indicate whether a reflow process has occurred to the embedded storage device.

Abstract: A temperature-controlled storage module is disclosed. In one embodiment, a storage module is provided comprising a memory, a temperature sensor, a thermoelectric cooler, and a controller. The controller compares a temperature reading from the temperature sensor to a target temperature. If the temperature reading differs from the target temperature, the controller activates the thermoelectric cooler. For example, if the temperature reading is higher than the target temperature, the thermoelectric cooler can be activated to cool the memory. This allows the memory (e.g., NAND die(s)) to operate in a narrow range of temperatures providing better system tradeoffs on memory (e.g., NAND) characteristics.

Abstract: A temperature-controlled storage module is disclosed that cools memory prior to a data burst. In one embodiment, a storage module is provided comprising a memory, a temperature sensor, a thermoelectric cooler, and a controller. The controller determines that a host in communication with the storage module is about to send a burst of data and then activates the thermoelectric cooler to cool the memory. The controller can determine that the host is about to send a burst of data either from a notification from the host or by making an inference based on write activity from the host over a period of time. This enables higher parallelism during the burst, hence improving the burst's performance.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A data storage device includes a memory and a controller coupled to the non-volatile memory. The controller is coupled to a communication interface that is configured to enable communication with a host device. The controller is configured to send a signal via a first connection of the communication interface and to send a corresponding clock signal via a second connection of the communication interface. The signal is compliant with a communication protocol that specifies that the first connection of the communication interface carries the signal while the second connection of the communication interface carries the clock signal. The first connection is testable to measure the signal to generate data indicating transitions of the signal. The data excludes measurements of the clock signal. The data is analyzable to detect an indication defined by the communication protocol and to determine an estimated bit sequence of the signal.

Abstract: Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.

Abstract: A system and method for data tag sharing is disclosed. A host system may provide a storage system with information that identifies a set of logical addresses as pointing to data that is cold, which may mean that the data has not been written to within a threshold time period, such as a year. The storage system may process the data stored at physical locations corresponding to the set of logical addresses as cold data based on receipt of the information from the host system.