Abstract: The present invention relates to a relay protective device, a construction machine, a relay protection control method and apparatus, and a computer readable storage medium.

Abstract: A semi-submersible floating wind power generator includes a wind power generator set, a post device, a load carrying device and a mooring device. The wind power generator set is disposed at a first end of the post device. The load carrying device is disposed at a second end of the post device. The mooring device is disposed at the second end of the post device. The post device includes a main post and multiple auxiliary posts. The main post is disposed in parallel with the multiple auxiliary posts, and second ends of the multiple auxiliary posts are aligned such that the second ends of the multiple auxiliary posts form a first plane, and the second end of the main post is disposed at a position closer to the first end of the main post than the first plane.

Abstract: A liquid crystal light-control panel includes a first array substrate and a cover plate opposite to each other, and a plurality of support pillars disposed between the first array substrate and the cover plate. The first array substrate includes a first substrate and a plurality of transistors disposed on the first substrate. The cover plate includes a second substrate and a light-shielding layer, including a plurality of first light-shielding blocks in one-to-one correspondence with the plurality of support pillars and a plurality of second light-shielding blocks in one-to-one correspondence with the plurality of transistors, disposed on the second substrate. An orthographic projection of the support pillar onto the first substrate is within an orthographic projection of the corresponding first light-shielding block onto the first substrate.

Abstract: A gesture recognition method, apparatus and system based on coupling capacitance, which are configured to solve the technical problem in the prior art of it not being possible to recognize a complex gesture due to the fact that the coordinates of a manipulation body on a three-dimensional plane cannot be determined.

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

Abstract: A heterogeneous image registration method includes: performing edge detection on collected images, in combination with a curvature scale space strategy to extract contour curved segments in an edge image. Implementing a feature point detection strategy based on global and local curvature detecting feature points in the contour curved segments, and obtaining the nearest minimum local curvature of the feature points pointing to starting and end points of the contour, respectively. Calculating the number of neighborhood sampling points and neighborhood auxiliary feature points of neighborhoods on both edges of each of the feature points according to the nearest minimum local curvature. Using neighborhood auxiliary feature points and feature points to form a feature triangle, calculating an angle bisector vector and a main direction corresponding to the feature point in the feature triangle.

Abstract: The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.

Abstract: A transparent structure comprising a transparent substrate, a transparent resistive heating element mounted on the substrate, metal traces forming electrodes arranged to be in electrical contact with the transparent heating element and positioned around boundaries of a heated region defining a circuit for electrical flow through the transparent resistive heating element, and a power source connected to the electrodes with the capability of delivering at least 1 volts to the electrodes wherein the transparent resistive heating element comprises a sparse metal conductive layer comprising nanowire segments of noble metal coated silver having a sheet resistance from about 1 Ohms/sq. to about 300 Ohms/sq and having an unpatterned area of at least about 0.25 cm2.

Abstract: Examples described herein relate to circuitry to allocate an Non-volatile Memory Express (NVMe) bounce buffer in virtual memory that is associated with an NVMe command and perform an address translation to an NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target. In some examples, the circuitry is to translate the virtual address to a physical address for the NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target.

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

Abstract: Circuits and methods for determining a maximum bias for computing softmax on a tensor include a processor circuit configured to transform in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements. The respective power-of-two element from element xt of the tensor is pt, pt=(xt*log2e), and pt has an integer part and a fraction part. A first comparison circuit (204) is configured to determine respective group-level biases for the groups. The group-level bias of groupm is dm, and dm is an integer part of a maximum of the power-of-two elements of groupm. A second comparison circuit is configured to determine a greatest one of the respective group-level biases to be a tensor-level bias, dmax.

Abstract: A network interface device executes an input/output (I/O) virtualization manager to identify a virtual device defined to include resources of a particular virtual functions in a plurality of virtual functions associated with a physical function of a device. An operation is identified to be performed between the virtual device and a system image hosted by a host system coupled to the network interface device. The network interface device emulates the virtual device in the operation using the I/O virtualization manager.

Abstract: The present invention relates to a relay protective device, a construction machine, a relay protection control method and apparatus, and a computer readable storage medium.

Abstract: An output rule specified via a distributed system execution request data structure for a requested calculation is determined, and a current rule is initialized to the output rule. A rule lookup table data structure is queried to determine a set of matching rules, corresponding to the current rule. The best matching rule is selected. A logical dependency graph (LDG) data structure is generated by adding LDG nodes and LDG edges corresponding to the best matching rule, precedent rules of the best matching rule, and precedent rules of each precedent rule. An execution complexity gauge value and a set of distributed worker processes are determined. The LDG data structure is divided into a set of subgraphs. Each worker process is initialized with the subgraph assigned to it. Execution of the requested calculation is coordinated and a computation result of the LDG node corresponding to the output rule is obtained.

Abstract: Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces. In some examples, the device interface is compatible with Peripheral Component Interconnect Express (PCIe) and the storage configuration circuitry is accessible as a physical function (PF) or a virtual function (VF).

Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.

Abstract: Examples described herein relate to a network interface that includes an initiator device to determine a storage node associated with an access command based on an association between an address in the command and a storage node. The network interface can include a redirector to update the association based on messages from one or more remote storage nodes. The association can be based on a look-up table associating a namespace identifier with prefix string and object size. In some examples, the access command is compatible with NVMe over Fabrics. The initiator device can determine a remote direct memory access (RDMA) queue-pair (QP) lookup for use to perform the access command.

Abstract: Examples described herein relate to circuitry configured to generate at least one virtual device interface to utilize the processor circuitry and provide the at least one virtual device interface to a server to assign to a process to provide the process with capability to utilize the processor circuitry. In some examples, the processor circuitry is to perform one or more of local area network access, cryptographic processing, and/or storage access. In some examples, the storage access comprises access to one or more Non-volatile Memory Express (NVMe) devices.

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

Abstract: Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.