Abstract: A semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate comprising a first surface and a second surface opposite to each other; forming, on the first surface, a first transistor structure comprising a first channel layer, a first gate structure disposed on the first channel layer, and a first source-drain epitaxial layer disposed on two lateral sides of the first gate structure; providing, on the second surface, a second transistor structure comprising a second channel layer, a second gate structure disposed on the second channel layer, and a second source-drain epitaxial layer disposed on two lateral sides of the second gate structure; forming, in the second source-drain epitaxial layer and the substrate, a first conductive plug electrically connected to the first source-drain epitaxial layer; and forming a first interconnection layer on the first conductive plug and the second gate structure.

Abstract: A display panel includes an active area; a fanout region; and a bonding region located on one side of the fanout region away from the active area. A driver chip is disposed in the bonding region. The driver chip includes a first side edge adjacent to the fanout region, a second side edge opposite to the first side edge, and two third side edges. The driver chip includes a plurality of output terminals disposed close to the first side edge. The display panel includes: a plurality of fanout lines located in the fanout region; and a plurality of gull-wing lines located in the bonding region. Part of the fanout lines extend from the fanout region to a region where the first side edge is located, and are electrically connected to the output terminals. Another part of the fanout lines are electrically connected to the output terminals via the gull-wing lines.

Abstract: A display substrate and a display device are provided. The display substrate has a display area and a peripheral area surrounding the display area. The display substrate includes a first common voltage line, a second common voltage line and an integrated circuit. The first common voltage line is provided in the peripheral area and at least partially surrounds the display area; the second common voltage line is provided in the peripheral area, located on a side of the first common voltage line away from the display area, and at least partially surrounds the display area; the integrated circuit is provided in the peripheral area, and located on a first side of the display area, configured to provide first signals to the first and second common voltage line during a display stage, and provide second signals to the first and second common voltage line during a touch stage.

Abstract: The present disclosure relates to a device and method for continuous mixing of a solid drag reducer. The device for continuous mixing of a solid drag reducer comprises a raw material storage device (1), a pneumatic raw material delivery device (2), a power device (3), a flow testing device (4) and a dissolving device (5). The method for continuous mixing of a solid drag reducer uses the device for continuous mixing of a solid drag reducer, which can realize continuous mixing of the solid drag reducer during large-scale volume fracturing.

Abstract: Battery materials and manufacturing methods therefor, and secondary batteries. The molecular general formula of the battery material may include A3V2-xEx(P1-yLyO4)3, wherein the element E represents a doping element that replaces the element V, and comprises at least one of a transition metal element, a rare earth element, Mg, and Sr; the element L represents a doping element that replaces the element P, and comprises at least one of B, Al, Ga, Si, Ge, and Sn; the element A represents an alkali metal element; 0?x?1 and 0<y??; and when the element L is the element B, x is not 0.

Abstract: Positive electrode active materials and preparation methods therefor, positive electrodes comprising a positive electrode active material, secondary batteries comprising a positive electrode, and electric devices comprising a secondary battery. The general formula of the positive electrode active material comprises A3V2-xMx(P1-yEyO4)3, wherein A represents an alkali metal element; M represents a doping element that substitutes for V; M comprises one or more of transition metal elements and rare earth elements; E represents a doping element that substitutes for P; E comprises one or more of As, Sb, and Bi; and 0?x?1, and 0<y?1/3.

Abstract: A liquid crystal light-control panel includes a first array substrate and a cover plate opposite to each other, and a plurality of support pillars disposed between the first array substrate and the cover plate. The first array substrate includes a first substrate and a plurality of transistors disposed on the first substrate. The cover plate includes a second substrate and a light-shielding layer, including a plurality of first light-shielding blocks in one-to-one correspondence with the plurality of support pillars and a plurality of second light-shielding blocks in one-to-one correspondence with the plurality of transistors, disposed on the second substrate. An orthographic projection of the support pillar onto the first substrate is within an orthographic projection of the corresponding first light-shielding block onto the first substrate.

Abstract: Battery materials and preparation methods therefor, and secondary batteries. The general molecular formula of a battery material may include A3V2-xEx(P1-yMyO4)3, wherein the element A represents an alkali metal element; the element E represents a doping element that substitutes for V, and comprises at least one of transition metal elements, rare earth elements, Mg and Sr; the element M represents a doping element that substitutes for P, and comprises at least one of S and Se; and 0?x?1, and 0<y??.

Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

Abstract: A display substrate and a display device are provided. The display substrate has a display area and a peripheral area surrounding the display area. The display substrate includes a first common voltage line, a second common voltage line and an integrated circuit. The first common voltage line is provided in the peripheral area and at least partially surrounds the display area; the second common voltage line is provided in the peripheral area, located on a side of the first common voltage line away from the display area, and at least partially surrounds the display area; the integrated circuit is provided in the peripheral area, and located on a first side of the display area, configured to provide first signals to the first and second common voltage line during a display stage, and provide second signals to the first and second common voltage line during a touch stage.

Abstract: Provided is an array substrate, including a substrate. The substrate includes a display region and a peripheral region surrounding the display region. The display region includes a plurality of pixel regions arranged in arrays. The array substrate further includes a plurality of GOA units and a plurality of gate lines. The plurality of GOA units are arranged along a first direction. The peripheral region includes a data pad (DP) region and a data pad opposite (DPO) region that are arranged opposite to each other along a second direction on two sides of the display region. The plurality of GOA units are within the DPO region, the plurality of gate lines are within the display region, and the plurality of GOA units are electrically connected to the plurality of gate lines. The first direction is intersected with the second direction.

Abstract: The present disclosure provides a driving module and a display device. The driving module includes a serial-parallel conversion circuit and a data providing circuit, the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal. According to the embodiments of the present disclosure, it is able to achieve display through relying on serial input signals and other signals provided by a system without a display chip.

Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

Abstract: Provided are a display substrate, a display module and a display device. The display substrate has a display region and a test pad region, and includes: a base; at least one pad on the base and in the test pad region; a first spacing layer on a side of the pad away from the base; multiple support parts and at least one test signal line in the test pad region and on a side of the first spacing layer away from the base, each test signal line has one end connected to one pad and another end connected to an array test device; at least two of the support parts are arranged along a first direction intersecting a direction pointing to the test pad region from the display region, each support part has a support end projecting from a surface of the test signal line away from the base.

Abstract: A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.

Abstract: A display substrate includes a display area, which includes a plurality of sub-areas arranged in a first direction. In at least one sub-area, the display substrate further includes a base substrate, a plurality of sub-pixels arranged in a fourth direction, a data line, and a first touch line extending in the fourth direction. The of sub-pixels include a first sub-pixel and a second sub-pixel, at least one first sub-pixel extends in a second direction, and at least one second sub-pixel extends in a third direction; The first, second, third and fourth directions intersect with one another. The data line is electrically connected to the sub-pixels through a plurality of input transistors. At least one input transistor includes a first electrode electrically connected to the sub-pixel. Orthographic projections of the first touch line and the first electrode on the base substrate do not overlap with each other.

Abstract: A display substrate and a display device are provided. The display substrate has a display area and a peripheral area surrounding the display area. The display substrate includes a first common voltage line, a second common voltage line and an integrated circuit. The first common voltage line is provided in the peripheral area and at least partially surrounds the display area; the second common voltage line is provided in the peripheral area, located on a side of the first common voltage line away from the display area, and at least partially surrounds the display area; the integrated circuit is provided in the peripheral area, and located on a first side of the display area, configured to provide first signals to the first and second common voltage line during a display stage, and provide second signals to the first and second common voltage line during a touch stage.

Abstract: Provided is an array substrate, including: a substrate including a display region, a wiring region, and a circuit region that are successively adjacent; a plurality of pixels disposed in the display region; a common electrode line disposed in the wiring region and including a plurality of cutouts spaced apart; a plurality of gate lines disposed in the display region and the wiring region; a plurality of gate leads disposed in the circuit region and the wiring region; and a gate drive circuit, disposed in the circuit region and coupled to the plurality of gate leads, wherein the plurality of gate leads are connected to the plurality of gate lines by a connection portion disposed within the cutout, and the plurality of gate lines are coupled to the plurality of pixels.

Abstract: The array substrate includes: a base substrate including a display region and a peripheral region; a plurality of data signal lines; a plurality of touch signal lines; a driving chip, where the peripheral region includes a fan-out region, the fan-out region includes a first sub-region and a second sub-region, and the first sub-region is closer to the display region than the second sub-region; the array substrate further includes a plurality of data signal leads located in the fan-out region and a plurality of touch signal leads located in the fan-out region; the data signal lead includes a first data signal sub-lead located in the first sub-region and a second data signal sub-lead located in the second sub-region, and the touch signal lead includes a first touch signal sub-lead located in the first sub-region and a second touch signal sub-lead located in the second sub-region.

Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.