Abstract: A display substrate includes a display area, which includes a plurality of sub-areas arranged in a first direction. In at least one sub-area, the display substrate further includes a base substrate, a plurality of sub-pixels arranged in a fourth direction, a data line, and a first touch line extending in the fourth direction. The of sub-pixels include a first sub-pixel and a second sub-pixel, at least one first sub-pixel extends in a second direction, and at least one second sub-pixel extends in a third direction; The first, second, third and fourth directions intersect with one another. The data line is electrically connected to the sub-pixels through a plurality of input transistors. At least one input transistor includes a first electrode electrically connected to the sub-pixel. Orthographic projections of the first touch line and the first electrode on the base substrate do not overlap with each other.

Abstract: Provided is an array substrate, including: a substrate including a display region, a wiring region, and a circuit region that are successively adjacent; a plurality of pixels disposed in the display region; a common electrode line disposed in the wiring region and including a plurality of cutouts spaced apart; a plurality of gate lines disposed in the display region and the wiring region; a plurality of gate leads disposed in the circuit region and the wiring region; and a gate drive circuit, disposed in the circuit region and coupled to the plurality of gate leads, wherein the plurality of gate leads are connected to the plurality of gate lines by a connection portion disposed within the cutout, and the plurality of gate lines are coupled to the plurality of pixels.

Abstract: A display substrate and a display device are provided. The display substrate has a display area and a peripheral area surrounding the display area. The display substrate includes a first common voltage line, a second common voltage line and an integrated circuit. The first common voltage line is provided in the peripheral area and at least partially surrounds the display area; the second common voltage line is provided in the peripheral area, located on a side of the first common voltage line away from the display area, and at least partially surrounds the display area; the integrated circuit is provided in the peripheral area, and located on a first side of the display area, configured to provide first signals to the first and second common voltage line during a display stage, and provide second signals to the first and second common voltage line during a touch stage.

Abstract: The array substrate includes: a base substrate including a display region and a peripheral region; a plurality of data signal lines; a plurality of touch signal lines; a driving chip, where the peripheral region includes a fan-out region, the fan-out region includes a first sub-region and a second sub-region, and the first sub-region is closer to the display region than the second sub-region; the array substrate further includes a plurality of data signal leads located in the fan-out region and a plurality of touch signal leads located in the fan-out region; the data signal lead includes a first data signal sub-lead located in the first sub-region and a second data signal sub-lead located in the second sub-region, and the touch signal lead includes a first touch signal sub-lead located in the first sub-region and a second touch signal sub-lead located in the second sub-region.

Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, sub-pixels, signal lines and signal line connection lines. The base substrate includes a first region and a second region, and a number of the sub-pixels along a first direction in the first region is larger than a number of the sub-pixels along the first direction in the second region. The signal line connection lines are electrically connected with the signal lines located in the second region. The display substrate further includes overlapping traces disposed at intervals and located in a layer different from that of the signal line connection lines. An orthographic projection of at least one of the signal line connection lines on the base substrate is completely within an orthographic projection of at least one of the overlapping traces on the base substrate.

Abstract: A liquid crystal light-control panel includes a first array substrate and a cover plate opposite to each other, and a plurality of support pillars disposed between the first array substrate and the cover plate. The first array substrate includes a first substrate and a plurality of transistors disposed on the first substrate. The cover plate includes a second substrate and a light-shielding layer, including a plurality of first light-shielding blocks in one-to-one correspondence with the plurality of support pillars and a plurality of second light-shielding blocks in one-to-one correspondence with the plurality of transistors, disposed on the second substrate. An orthographic projection of the support pillar onto the first substrate is within an orthographic projection of the corresponding first light-shielding block onto the first substrate.

Abstract: A gesture recognition method, apparatus and system based on coupling capacitance, which are configured to solve the technical problem in the prior art of it not being possible to recognize a complex gesture due to the fact that the coordinates of a manipulation body on a three-dimensional plane cannot be determined.

Abstract: A display panel includes an active area; a fanout region; and a bonding region located on one side, away from the active area, of the fanout region. A driver chip is disposed in the bonding region. The driver chip includes a first side edge adjacent to the fanout region, a second side edge opposite to the first side edge, and two third side edges. The driver chip includes a plurality of output terminals disposed close to the first side edge. The display panel includes: a plurality of fanout lines located in the fanout region; and a plurality of gull-wing lines located in the bonding region. Part of the fanout lines extend from the fanout region to a region where the first side edge is located, and are electrically connected to the output terminals. Another part of the fanout lines are electrically connected to the output terminals via the gull-wing lines.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; and a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); where the pattern unit (171a) further includes a second bump (1712) located within a central area surrounded by each of the first bumps (1710), and the spacing groove (1711) on a same side of the first bump (1710) and the second bump (1712) is arranged in a non-straight shape.

Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.

Abstract: The present disclosure provides a display substrate, a display module and a display device.

Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: A gesture recognition method, apparatus and system based on coupling capacitance, which are configured to solve the technical problem in the prior art of it not being possible to recognize a complex gesture due to the fact that the coordinates of a manipulation body on a three-dimensional plane cannot be determined.

Abstract: A power control method for a hair dryer, includes: determining a target range of a working parameter of a heating element of the hair dryer according to a target power range of the hair dryer; the working parameter comprising a time characteristic parameter during which the heating element of the hair dryer is turned on in a predetermined period; and controlling the working parameter of the heating element to be kept within the target range, so that a power of the hair dryer is kept within the target power range. A method for calibrating a temperature control parameter of the hair dryer and a device for calibrating a temperature control parameter of the hair dryer are also disclosed.