Patents by Inventor Yael Duek-Golan

Yael Duek-Golan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems for total coverage analysis and ranking of circuit designs
    Patent number: 8214782
    Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: July 3, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Swapnajit Chakraborti, Sandeep Pagey, Boris Gommershtadt, Yael Duek-Golan
  • Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs
    Patent number: 7886242
    Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: February 8, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Swapnajit Chakraborti, Sandeep Pagey, Boris Gommershtadt, Yael Duek-Golan