Abstract: There is disclosed a state machine made up of a delay slot path and a no operation path, both made up of nodes with arcs connecting between them. There are arcs between the nodes of the delay slot path and the nodes of the no operation path. The number of nodes in the no operation path is equivalent to the number of available delay slots. The path taken for a specific instruction along the delay slot path, the no operation path and the arcs depends on the number of delay slots which the specific instruction utilizes. There is also disclosed a method for executing non-sequential instructions as performed by the state machine of the present invention.

Abstract: A processor made up of a computation unit, an accumulator unit, a saturation determination unit and a saturation unit. The computation unit operates on one or more operands of W bits. The accumulator unit stores the output of the computation unit, in W bits. The saturation determination unit detects overflow in parallel with latching of the output of the computation unit. Overflow occurs when the operand latched by the accumulator represents a number having more than A significant bits, where A is less than W. The saturation unit provides saturation operands to the computation unit when the operand latched in the accumulator unit represents a number having more than A significant bits. Furthermore, the processor has saturation operands of either (+2A−1−1) or −2A−1. A method for using the processor is also disclosed.

Abstract: A processor coupled to a memory for providing a pointer in order to access a corresponding memory address, the pointer being updated by adding a predetermined increment according to logic integral with the processor. A method is disclosed for updating the pointer to a value other than that dictated by the processor logic so as to access an arbitrary memory address dictated by an application program accessing the processor. The method comprises disabling the logic in respective of the pointer, processing the application program so as generate a successive memory address for accessing the memory, and setting the pointer to the successive memory address instead of incrementing the pointer by the predetermined increment dictated by the logic.

Abstract: A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words.

Abstract: A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words.

Abstract: A data processing and addressing unit for processing a set of either first or second type instructions having associated therewith operands stored in a single memory bank and operands stored in two memory banks, respectively. First and second memory banks are mapped in continuous memory address space such that a bottom address of the second memory bank is contiguous with a top address of the first memory bank. A method is employed for mapping the first and second memory banks so as to permit memory expansion or contraction while permitting the first and second memory banks to be configured as a single continuous buffer or as two distinct buffers, as required.

Abstract: An improved cyclical buffer having an integer M number of memory locations in respect of which a number STEP of consecutive memory locations are required to be accessed in a single operation and having a predetermined START location defining an initial memory location to be accessed. M is constrained to be an integer multiple of STEP and the k least significant bits of START are zero where k is the minimal integer satisfying the relation 2.sup.k >M-.vertline.STEP.vertline.. The result is the same as the general MODULO algorithm employed in conventional cyclical buffers but without the cost of implementing the complete MODULO function. An apparatus for generating successive addresses involves an ADDER and a k-bit COMPARATOR coupled via a MULTIPLEXER to an address register such that the k-least significant bits of the ADDER or M-.vertline.STEP.vertline. or 0 is fed to the k-least significant bits of the address register depending on the output of the k-bit COMPARATOR.