Abstract: A delay line structure and a delay jitter correction method thereof are provided. The delay line structure comprises N delay units and N selectors. An output end of the N?1th delay unit is connected to a first input end of the N?1th selector and an input end of the Nth delay unit respectively, the N?1th selector inputs the N?1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N?1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals.

Abstract: A delay line structure and a delay jitter correction method thereof are provided. The delay line structure comprises N delay units and N selectors. An output end of the N-1th delay unit is connected to a first input end of the N-1th selector and an input end of the Nth delay unit respectively, the N-1th selector inputs the N-1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N-1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals.

Abstract: A method and apparatus of clock recovery is disclosed. A communications device matches the frequency of a local clock signal with the frequency of a transmit clock signal of a transmitting device based on a first set of signals received from the transmitting device during a low-speed information exchange. The low-speed information exchange may correspond to an autonegotiation operation, wherein each of the transmitting device and the communications device declares its communication capabilities to the other device. The communications device then determines a frequency offset to be applied to the local clock signal during a high-speed data communication with the transmitting device. During the high-speed communication, the communications device may apply the frequency offset to the local clock signal and match the phase of the receive clock signal with the phase of the transmit clock signal based on a second set of signals received from the transmitting device.

Abstract: A method and apparatus of clock recovery is disclosed. A communications device matches the frequency of a local clock signal with the frequency of a transmit clock signal of a transmitting device based on a first set of signals received from the transmitting device during a low-speed information exchange. The low-speed information exchange may correspond to an autonegotiation operation, wherein each of the transmitting device and the communications device declares its communication capabilities to the other device. The communications device then determines a frequency offset to be applied to the local clock signal during a high-speed data communication with the transmitting device. During the high-speed communication, the communications device may apply the frequency offset to the local clock signal and match the phase of the receive clock signal with the phase of the transmit clock signal based on a second set of signals received from the transmitting device.

Abstract: A method for operating a receiver is disclosed. The receiver may receive, over a channel from a transmitter, a first data bit at a first period of time. The receiver may receive, over the channel, a second data bit at a second period of time subsequent to the first period of time. The first and second data bits each have either a first logical value corresponding to a voltage greater than zero volts or a second logical value corresponding to a voltage less than or equal to zero volts. The receiver performs a coefficient adaptation operation, using the first data bit, to adjust one or more coefficients of a decision feedback equalizer of the receiver only when the logical value of the first data bit is equal to the logical value of the second data bit.