Patents by Inventor Yai-Fen Lin
Yai-Fen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6410957Abstract: A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in forming the floating gate, and also using to advantage a so-called “smiling effect” which is normally taught away. The smiling effect, or an uneven thickening of an oxide layer, comes into play while growing interpoly oxide where concurrently the oxidation of the polysilicon gate advances in such a manner so as to form a sharp and reliable poly tip. The invention is also directed to providing a split gate flash memory cell having a thin floating gate and a poly tip therein.Type: GrantFiled: November 16, 2000Date of Patent: June 25, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Hung-Cheng Sung
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Patent number: 6396112Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.Type: GrantFiled: February 20, 2001Date of Patent: May 28, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Yai-Fen Lin, Hung-Cheng Sung
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Publication number: 20020055205Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.Type: ApplicationFiled: December 31, 2001Publication date: May 9, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yai-Fen Lin, Chang Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh
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Patent number: 6385089Abstract: In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.Type: GrantFiled: May 8, 2001Date of Patent: May 7, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Cheng Sung, Din-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin
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Patent number: 6380583Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.Type: GrantFiled: October 6, 2000Date of Patent: April 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo, Hung-Cheng Sung, Jack Yeh
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Patent number: 6380035Abstract: A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line is disclosed. A relatively thin polygate is formed so as to decrease the growth of the protrusion of conventional gate bird's beak (GBB) to a smaller and sharper tip. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell.Type: GrantFiled: November 16, 2000Date of Patent: April 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Cheng Sung, Di-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin
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Patent number: 6358796Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.Type: GrantFiled: April 15, 1999Date of Patent: March 19, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chang-Song Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh
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Patent number: 6355527Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.Type: GrantFiled: May 19, 1999Date of Patent: March 12, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Jack Yeh, Di-Son Kuo
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Publication number: 20020027241Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.Type: ApplicationFiled: August 2, 2001Publication date: March 7, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu
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Publication number: 20020016039Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell.Type: ApplicationFiled: August 10, 2001Publication date: February 7, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chung-Ke Yeh, Wen-Ting Chu, Di-Son Kuo
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Patent number: 6344997Abstract: In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.Type: GrantFiled: May 17, 2001Date of Patent: February 5, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Cheng Sung, Din-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin
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Patent number: 6333228Abstract: A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved.Type: GrantFiled: March 24, 2000Date of Patent: December 25, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Yeh, Wen-Ting Chu, Di-Son Kuo
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Patent number: 6326660Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the float gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.Type: GrantFiled: March 13, 2000Date of Patent: December 4, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo
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Patent number: 6312989Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell.Type: GrantFiled: January 21, 2000Date of Patent: November 6, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Wen-Ting Chu, Di-Son Kuo
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Patent number: 6309928Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.Type: GrantFiled: December 10, 1998Date of Patent: October 30, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu
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Publication number: 20010033513Abstract: In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory..Type: ApplicationFiled: May 17, 2001Publication date: October 25, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Hung-Cheng Sung, Din-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin
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Publication number: 20010028577Abstract: In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.Type: ApplicationFiled: May 8, 2001Publication date: October 11, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Hung-Cheng Sung, Din-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin
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Publication number: 20010029076Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.Type: ApplicationFiled: March 27, 2001Publication date: October 11, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Yai-Fen Lin, Shiou-Hann Liaw, Di-Son Kuo, Juang-Ke Yeh
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Publication number: 20010026973Abstract: A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.Type: ApplicationFiled: June 8, 2001Publication date: October 4, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chung-Ker Yeh, Hung-Cheng Sung, Di-Son Kuo, Chia-Ta Hsieh, Yai-Fen Lin
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Publication number: 20010017387Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.Type: ApplicationFiled: February 20, 2001Publication date: August 30, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Yai-Fen Lin, Hung-cheng Sung