Patents by Inventor Yai-Fen Liu

Yai-Fen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Split gate flash memory device with shrunken cell and source line array dimensions
    Patent number: 6538276
    Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: March 25, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Ta Hsieh, Yai-Fen Liu, Hung-Cheng Sung, Di-Son Kuo
  • Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line and device manufactured thereby
    Publication number: 20010015455
    Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.
    Type: Application
    Filed: January 8, 2001
    Publication date: August 23, 2001
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chia-Ta Hsieh, Yai-Fen Liu, Hung-Cheng Sung, Di-Son Kuo