Patents by Inventor Yaichiro Miura

Yaichiro Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7871871
    Abstract: In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: January 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masanobu Hishiki, Yaichiro Miura, Hiroshi Kawashima, Katsuhiro Mitsuda
  • Publication number: 20090221105
    Abstract: In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 3, 2009
    Inventors: Masanobu Hishiki, Yaichiro Miura, Hiroshi Kawashima, Katsuhiro Mitsuda