Abstract: An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.

Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.

Abstract: A bistable cell includes a pair of inverters and multiple pairs of cross-coupled tristate buffers. Each pair of tristate buffers can be individually selected to implement an entropy harvesting state for the bistable cell. Each of the tristate buffers generally has lower strength than the inverters but the inverter-to-buffer strength ratio can be configured through selective use of one or more of the tristate buffer pairs. The resulting entropy harvesting state behavior can be varied based on the inverter-to-buffer strength ratio in terms of greater randomness of the output bits or decreased power consumption.