Abstract: A storage system and method are provided for hit-rate-score-based selective prediction of future random read commands. In one embodiment, a storage system is provided comprising a memory configured to store a prior read command data structure, the prior read command data structure comprising a hit-rate score field. The storage system receives a current read command; generates a search sequence of read commands comprising the current read command and at least one prior read command; calculates an index value based on the search sequence; reads a hit-rate score from the hit-rate score field of an entry of the prior read command data structure identified by the index value; determines whether the hit-rate score is less than a threshold; and in response to determining that the hit-rate score is less than the threshold, updates the prior read command data structure with the search sequence. Other embodiments are provided.

Abstract: A storage system and method are provided for hit-rate-score-based selective prediction of future random read commands. In one embodiment, a storage system is provided comprising a memory configured to store a prior read command data structure, the prior read command data structure comprising a hit-rate score field. The storage system receives a current read command; generates a search sequence of read commands comprising the current read command and at least one prior read command; calculates an index value based on the search sequence; reads a hit-rate score from the hit-rate score field of an entry of the prior read command data structure identified by the index value; determines whether the hit-rate score is less than a threshold; and in response to determining that the hit-rate score is less than the threshold, updates the prior read command data structure with the search sequence. Other embodiments are provided.

Abstract: A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (HMB) before transitioning to a low-power state, and uses the resume data stored within the HMB to resume operation from the low-power state. The memory device may be configured to pre-populate the HMB with resume data prior to transitioning to the low-power state. In some embodiments, the disclosed memory device is configured to gradually resume from the low-power state, which may comprise resuming services of the memory device in the order such services are required during the resume process.

Abstract: Systems and methods for monitoring a regulated voltage output for current consumption are disclosed. An analog component senses the current at the regulated voltage output and converts the sensed current into a digital representation, which is indicative of the sensed current. A digital component inputs and analyzes the digital representation to determine whether to generate an interrupt. The interrupt is indicative to an electronic device, which is using the regulated voltage, to modify its operation. For example, the digital component may analyze the digital representation by counting a number of system clock cycles during a part of the digital representation. The counted number of clock cycles may be compared with a threshold, which may be predetermined or dynamically selected, to determine whether to generate an interrupt. Thus, the sensed current from the regulated voltage output may be used to determine whether to modify operation of the electronic device.

Abstract: A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (HMB) before transitioning to a low-power state, and uses the resume data stored within the HMB to resume operation from the low-power state. The memory device may be configured to pre-populate the HMB with resume data prior to transitioning to the low-power state. In some embodiments, the disclosed memory device is configured to gradually resume from the low-power state, which may comprise resuming services of the memory device in the order such services are required during the resume process.

Abstract: A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence.

Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: Systems and methods for monitoring a regulated voltage output for current consumption are disclosed. An analog component senses the current at the regulated voltage output and converts the sensed current into a digital representation, which is indicative of the sensed current. A digital component inputs and analyzes the digital representation to determine whether to generate an interrupt. The interrupt is indicative to an electronic device, which is using the regulated voltage, to modify its operation. For example, the digital component may analyze the digital representation by counting a number of system clock cycles during a part of the digital representation. The counted number of clock cycles may be compared with a threshold, which may be predetermined or dynamically selected, to determine whether to generate an interrupt. Thus, the sensed current from the regulated voltage output may be used to determine whether to modify operation of the electronic device.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.

Abstract: A storage system may include a queue included in a memory and a controller configured to store commands received from a host in the queue. The queue may have a linked-list configuration. In response to a triggering event, the controller may take a snapshot of the queue, creating a snapshot queue. The snapshot queue may have a linear configuration. Subsequent analysis or parsing of queued information may be performed on the linear snapshot queue instead of the linked-list queue. Modifications to the linear snapshot queue may be corresponding made to the linked-list queue.

Abstract: A method, apparatus, and system may be provided for queuing storage commands. A command buffer may store storage commands for multiple command queues. Linked list controllers may control linked lists, where each one of the linked lists identifies the storage commands that are in a corresponding one of the command queues. The linked list storage memory may store next command pointers for the storage commands. A linked list element in any of the linked lists may include one of the storage commands stored in the command buffer and a corresponding one of the next command pointers stored in the linked list storage memory.

Abstract: A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: A storage system may include a queue included in a memory and a controller configured to store commands received from a host in the queue. The queue may have a linked-list configuration. In response to a triggering event, the controller may take a snapshot of the queue, creating a snapshot queue. The snapshot queue may have a linear configuration. Subsequent analysis or parsing of queued information may be performed on the linear snapshot queue instead of the linked-list queue. Modifications to the linear snapshot queue may be corresponding made to the linked-list queue.

Abstract: The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.

Abstract: A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence.