Abstract: A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.

Abstract: An arithmetic logic unit includes overflow trap logic for an integer-multiply instruction. A multiply unit multiplies a pair of n-bit operands together and produces a n+1 bit result. The low order n-bits are returned as the multiplication result. A first overflow logic unit examines the leading bits of both operands and counts the number of leading bits which are equal to respective sign bits. If the count is smaller than n, an overflow trap is signalled. If not, then a second logic unit examines bits n and n-1 of the result and signals an overflow trap if these bits are not equal.

Abstract: Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the LSB to the MSB, with a "0" being loaded into the LSB. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a "1". After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.