Abstract: In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.

Abstract: A counter circuit for an analog to digital converter includes: a plurality of counter stages configured to obtain an integer multiple of a digital gain for the analog to digital converter by bypassing at least one of the plurality of counter stages. An analog-to-digital converter includes at least one counter circuit, and an image sensor includes the analog-to-digital converter, which includes the counter circuit.

Abstract: In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.

Abstract: A counter circuit for an analog to digital converter includes: a plurality of counter stages configured to obtain an integer multiple of a digital gain for the analog to digital converter by bypassing at least one of the plurality of counter stages. An analog-to-digital converter includes at least one counter circuit, and an image sensor includes the analog-to-digital converter, which includes the counter circuit.

Abstract: A counter circuit for an analog to digital converter includes: a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal, counting phase depending on the state of the output clock at the end of the reset counting phase.