Patents by Inventor Yair Talker
Yair Talker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240003968Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: ApplicationFiled: September 17, 2023Publication date: January 4, 2024Inventors: Evelyn LANDMAN, Yahel DAVID, Eyal FAYNEH, Shai COHEN, Yair TALKER
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Patent number: 11762013Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: GrantFiled: April 16, 2019Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yahel David, Eyal Fayneh, Shai Cohen, Yair Talker
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Patent number: 11327523Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.Type: GrantFiled: February 24, 2020Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nassar, Yair Talker
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Publication number: 20220012395Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Inventors: Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB
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Patent number: 11132485Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: GrantFiled: June 19, 2019Date of Patent: September 28, 2021Assignee: PROTEANTECS LTD.Inventors: Evelyn Landman, Yair Talker, Eyal Fayneh, Yahel David, Shai Cohen, Inbar Weintrob
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Publication number: 20210173007Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.Type: ApplicationFiled: April 16, 2019Publication date: June 10, 2021Inventors: Evelyn LANDMAN, Yahel DAVID, Eyal FAYNEH, Shai COHEN, Yair TALKER
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Publication number: 20210165941Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.Type: ApplicationFiled: June 19, 2019Publication date: June 3, 2021Inventors: Evelyn LANDMAN, Yair TALKER, Eyal FAYNEH, Yahel DAVID, Shai COHEN, Inbar WEINTROB
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Publication number: 20200301465Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.Type: ApplicationFiled: February 24, 2020Publication date: September 24, 2020Applicant: Intel CorporationInventors: Eyal FAYNEH, Elias NASSAR, Inbar FALKOV, Ramkumar KRITHIVASAN, Vijay K. VUPPALADADIUM, Miguel A. CORVACHO HERNANDEZ, Samer NASSAR, Yair TALKER
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Patent number: 10571953Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.Type: GrantFiled: July 5, 2017Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Eyal Fayneh, Elias Nassar, Inbar Falkov, Ramkumar Krithivasan, Vijay K. Vuppaladadium, Miguel A. Corvacho Hernandez, Samer Nasser, Yair Talker
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Publication number: 20190011945Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.Type: ApplicationFiled: July 5, 2017Publication date: January 10, 2019Applicant: Intel CorporationInventors: Eyal FAYNEH, Elias NASSAR, Inbar FALKOV, Ramkumar KRITHIVASAN, Vijay K. VUPPALADADIUM, Miguel A. CORVACHO HERNANDEZ, Samer NASSER, Yair TALKER
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Patent number: 9965019Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.Type: GrantFiled: September 2, 2016Date of Patent: May 8, 2018Assignee: Intel CorporationInventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
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Publication number: 20160370839Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
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Patent number: 9459689Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.Type: GrantFiled: December 23, 2013Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
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Patent number: 9367080Abstract: Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a hardware logic unit, of the multiple hardware logic units, in response to a logic level of the enable signal, wherein the clock islands are part of a global clock distribution network and are operable to be enabled or disabled independently.Type: GrantFiled: December 22, 2011Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Alexander Gendler, Arye Albahari, Yair Talker, Yossi Ben Simon, Inbar Weintrob
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Publication number: 20150177824Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
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Publication number: 20130166939Abstract: Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a hardware logic unit, of the multiple hardware logic units, in response to a logic level of the enable signal, wherein the clock islands are part of a global clock distribution network and are operable to be enabled or disabled independently.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Inventors: Alexander Gendler, Arye Albahari, Yair Talker, Yossi Ben Simon, Inbar Weintrob