Abstract: An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

Abstract: Treatment of the positive electrode interface of an antifuse provides significantly improved on-state reliability. Treatments include, but are not limited to, a plasma etch using carbon tetrafluoride (CF.sub.4), a sputter clean using Argon, and wet chemical treatments using dimethyl formamide (and water) or a resist developer.

Abstract: Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Abstract: An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

Abstract: Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Abstract: A method of forming an antifuse in an integrated circuit having an insulating layer on a semiconductor substrate is provided. The method comprises forming a first metal interconnection layer on the insulating layer; forming a first barrier metal layer on the first metal interconnection layer; forming an amorphous silicon layer on the first barrier metal layer; forming another barrier metal layer atop the amorphous silicon layer; and forming a second metal interconnection layer on the second barrier metal layer. In at least one of the barrier metal forming steps, the barrier metal is formed by sputtering a barrier metal target which includes a semiconductor dopant, such as dopant.

Abstract: A method and structure for an improved antifuse in an integrated circuit having a sacrificial layer under a programming layer which forces a conductive link upon programming to be formed away from corner regions of the via structures. The method includes the unique step of forming an improved aperture or via with sides through an inter dielectric layer where the antifuse is to be located. The improved aperture or via exposes a portion of a metal interconnection line through a portion of sacrificial layer located away from the inter dielectric layer sides. Such improved method of forming the antifuse also provides a superior antifuse structure.