Patents by Inventor Yakov Royter
Yakov Royter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10515872Abstract: A transistor having an emitter, a base, and a collector, the transistor includes a substrate, a collector contact, a metallic sub-collector coupled to the collector contact, and the metallic sub-collector electrically and thermally coupled to the collector, and an adhesive layer between the substrate and the metallic sub-collector, the adhesive layer bonded to the substrate and in direct contact with the substrate and bonded to the metallic sub-collector and in direct contact with the metallic sub-collector, wherein the adhesive layer comprises an electrically conductive material.Type: GrantFiled: October 20, 2016Date of Patent: December 24, 2019Assignee: HRL Laboratories, LLCInventors: James Chingwei Li, Yakov Royter, Pamela R. Patterson, Donald A. Hitko
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Patent number: 9524872Abstract: A heterogeneous integrated circuit and method of making the same. An integrated circuit includes a surrogate substrate including a material selected from the group consisting of Group II, Group III, Group IV, Group V, and Group VI materials and their combinations; at least one active semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials; and at least one transferred semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials. The at least one active semiconductor device and the at least one transferred device are interconnected.Type: GrantFiled: April 28, 2011Date of Patent: December 20, 2016Assignee: HRL Laboratories, LLCInventors: Peter D. Brewer, Andrew T. Hunter, Yakov Royter
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Patent number: 9508552Abstract: A heterojunction bipolar transistor having an emitter, a base, and a collector, the heterojunction bipolar transistor including a metallic sub-collector electrically and thermally coupled to the collector wherein the metallic sub-collector comprises a metallic thin film, and a collector contact electrically connected to the metallic sub-collector.Type: GrantFiled: September 9, 2014Date of Patent: November 29, 2016Assignee: HRL Laboratories, LLCInventors: James Chingwei Li, Donald A. Hitko, Yakov Royter, Pamela R. Patterson
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Patent number: 9450022Abstract: A method for fabricating a digital memristor crossbar array includes applying a protective layer on at least a portion of a memristive layer. A method for fabricating an analog memristor crossbar array includes providing a self-aligning first electrode layer. An analog memristor includes a memristive layer bar arranged to self-align said second electrode on said memristive layer along its length.Type: GrantFiled: September 5, 2012Date of Patent: September 20, 2016Assignee: HRL Laboratories, LLCInventors: Dana C. Wheeler, Tahir Hussain, Yakov Royter, Eason F. Wang
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Patent number: 8900896Abstract: Fabrication of a photonic integrated circuit (PIC) including active elements such as a semiconductor optical amplifier (SOA) and passive elements such as a floating rib waveguide. Selective area doping through ion implantation or thermal diffusion before semiconductor epitaxial growth is used in order to define the contact and lateral current transport layers for each active device, while leaving areas corresponding to the passive devices undoped. InP wafers are used as the substrate which may be selectively doped with silicon.Type: GrantFiled: February 17, 2011Date of Patent: December 2, 2014Assignee: HRL Laboratories, LLCInventors: Yakov Royter, Rajesh D. Rajavel, Irina Ionova, Sophi Ionova
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Patent number: 8860092Abstract: A heterojunction bipolar transistor having an emitter, a base, and a collector, the heterojunction bipolar transistor including a metallic sub-collector electrically and thermally coupled to the collector wherein the metallic sub-collector comprises a metallic thin film, and a collector contact electrically connected to the metallic sub-collector.Type: GrantFiled: September 22, 2008Date of Patent: October 14, 2014Assignee: HRL Laboratories, LLCInventors: James Chingwei Li, Donald A. Hitko, Yakov Royter, Pamela R. Patterson
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Patent number: 7972936Abstract: A heterogeneous integrated circuit and method of making the same. An integrated circuit includes a surrogate substrate including a material selected from the group consisting of Group II, Group III, Group IV, Group V, and Group VI materials and their combinations; at least one active semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials; and at least one transferred semiconductor device including a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials. The at least one active semiconductor device and the at least one transferred device are interconnected.Type: GrantFiled: February 3, 2009Date of Patent: July 5, 2011Assignee: HRL Laboratories, LLCInventors: Peter D. Brewer, Andrew T. Hunter, Yakov Royter
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Patent number: 7875952Abstract: The present invention relates to a process for fabricating integrated circuit system. More particularly, the process allows for fabrication of highly integrated system-on-a-chip modules through heterogeneous integration of different semiconductor technologies wherein alignment targets on the base semiconductor are used for precise lateral positioning of device structures above.Type: GrantFiled: July 16, 2007Date of Patent: January 25, 2011Assignee: HRL Laboratories, LLCInventors: Kenneth R. Elliott, Peter David Brewer, Yakov Royter
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Patent number: 7695564Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.Type: GrantFiled: February 3, 2005Date of Patent: April 13, 2010Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Peter Deelman, Yakov Royter
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Patent number: 7569872Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.Type: GrantFiled: December 20, 2005Date of Patent: August 4, 2009Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Tahir Hussain, Yakov Royter
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Patent number: 7368765Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.Type: GrantFiled: December 20, 2005Date of Patent: May 6, 2008Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Tahir Hussain, Yakov Royter
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Patent number: 7067898Abstract: A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielectric layer and the width of the emitter is determined by the minimum resolution provided by the fabrication techniques and tools used to define features within the dielectric layer.Type: GrantFiled: May 25, 2004Date of Patent: June 27, 2006Assignee: HRL Laboratories, LLCInventors: Stephen Thomas, III, Yakov Royter