Abstract: A network device includes a memory configured to store a plurality of entries in respective locations in the memory, the plurality of entries corresponding to a trie data structure for performing a longest prefix match search. The network device also includes: a memory access engine configured to retrieve from a location in the memory, in a single memory lookup operation, i) longest prefix match information for a node corresponding to a network address in a header of a packet, and ii) pointer information that indicates a child node in the trie data structure. The network device also includes: a child node address calculator configured to use i) the longest prefix match information, and ii) the pointer information, to calculate a memory address of another location in the memory corresponding to the child node.

Abstract: A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.

Abstract: Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.

Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

Abstract: A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.

Abstract: A virtual address cache and a method for sharing data. The virtual address cache includes: a memory, adapted to store virtual addresses, task identifiers and data associated with the virtual addresses and the task identifiers; and a comparator, connected to the memory, adapted to determine that data associated with a received virtual address and a received task identifier is stored in the memory if at least a portion of the received virtual address equals at least a corresponding portion of a certain stored virtual address and a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks.

Abstract: A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.

Abstract: A virtual address cache comprising a comparator arranged to receive a virtual address for addressing data associated with a task and a memory, wherein the comparator is arranged to make a determination as to whether data associated with the received virtual address is stored in the memory based upon an indication that the virtual address is associated with data shared between a first task and a second task and a comparison of the received virtual address with an address associated with data stored in memory.

Abstract: Read/write conflicts in an instruction cache memory (11) are reduced by configuring the memory as two even and odd array sub-blocks (12,13) and adding an input buffer (10) between the memory (11) and an update (16). Contentions between a memory read and a memory write are minimised by the buffer (10) shifting the update sequence with respect to the read sequence. The invention can adapt itself for use in digital signal processing systems with different external memory behaviour as far as latency and burst capability is concerned.

Abstract: A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.

Abstract: A cache is used in the performance of one task that may be interrupted by another task. The first task results in the cache being loaded at least partially. The second task interrupts, but is preventing from thrashing the highest priority data. The highest priority data is not available for thrashing during the running of the second task. The second task may be interrupted as well. Similarly, the third task is prevented from thrashing the highest priority data of the second task and the first task. The third task can thrash all of the cache except that preserved for the first and second tasks. After the third task is completed, the second task can begin running again without having to reload the highest priority data. The first task is similarly completed.

Abstract: A processing system has a processor, a cache, and a fetch unit. If there is a miss in the cache, the fetch unit generates a fetch address for the miss in the cache for the purpose of retrieving the requested data from external memory and providing the data to the processor and loading the data in a location in a line in the cache. The fetch unit also generates additional prefetch addresses for addresses consecutive with the fetch address. The prefetch addresses continue to be generated for all of the locations in the line in the cache that are consecutive with the fetch address. The generation of prefetch addresses will be stopped if another requests arrives that is not part of the already generated prefetched addresses. Further, the outstanding prefetches will be terminated if the external memory can handle such termination.