Abstract: The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and the corresponding input terminal combinational logic and output terminal combinational logic. The construction of the said scan-chain includes the first multiplex module and the second multiplex module arranged with regard to each register, changing the operation mode of the said integrated circuit by controlling the first multiplex module and the second multiplex module, enabling the said integrated circuit to switch among the normal mode, holding mode and snapshot mode, and enabling the registers to form a scan-chain loop in the snapshot mode.

Abstract: A bus arbitration device includes a top arbiter, and the hierarchical bus arbitration device also includes a first arbiter. The said first arbiter arbitrates the first kind of requests, wherein the first kind of requests relates to the first kind of master units. The said second arbiter arbitrates the second kind of requests different from the first kind of requests, wherein the second kind of requests relates to the second kind of master units different from the first kind of master units. Wherein the said first arbiter and the said second arbiter are downward respectively from the top arbiter to form the hierarchical bus arbitration structure. Bus arbitration efficiency increases by this bus arbitration device.

Abstract: The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and the corresponding input terminal combinational logics and output terminal combinational logics. The construction of the said scan-chain includes the first multiplex module and the second multiplex module arranged with regard to each register, changing the operation mode of the said integrated circuit by controlling the first multiplex module and the second multiplex module, enabling the said integrated circuit to switch among the normal mode, holding mode and snapshot mode, and enabling the registers to form a scan-chain loop in the snapshot mode.