Patents by Inventor Yan-Bo SONG
Yan-Bo SONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071470Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: He-Zhou WAN, Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG
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Patent number: 11862231Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.Type: GrantFiled: October 26, 2022Date of Patent: January 2, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: He-Zhou Wan, Xiu-Li Yang, Mu-Yang Ye, Yan-Bo Song
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Publication number: 20230049698Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.Type: ApplicationFiled: October 26, 2022Publication date: February 16, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: He-Zhou WAN, Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG
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Patent number: 11514974Abstract: A memory device includes a word line driver. The word line driver is coupled through word lines to an array of bit cells. The word line driver includes a first driving circuit, a second driving circuit and a modulating circuit. The first driving circuit and the second driving circuit are configured to select a word line. The modulating circuit is coupled through the selected word line to the first driving circuit and the second driving circuit, and is configured to modulate at least one signal transmitted through the selected word line. The first driving circuit and the second driving circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions of the selected word line. The first voltage signal is substantially the same as the second voltage signal. A method is also disclosed herein.Type: GrantFiled: March 22, 2021Date of Patent: November 29, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: He-Zhou Wan, Xiu-Li Yang, Mu-Yang Ye, Yan-Bo Song
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Publication number: 20220367484Abstract: A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li YANG, He-Zhou WAN, Yan-Bo SONG
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Patent number: 11462551Abstract: A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell.Type: GrantFiled: April 8, 2021Date of Patent: October 4, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li Yang, He-Zhou Wan, Yan-Bo Song
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Publication number: 20220254404Abstract: A memory device includes a word line driver. The word line driver is coupled through word lines to an array of bit cells. The word line driver includes a first driving circuit, a second driving circuit and a modulating circuit. The first driving circuit and the second driving circuit are configured to select a word line. The modulating circuit is coupled through the selected word line to the first driving circuit and the second driving circuit, and is configured to modulate at least one signal transmitted through the selected word line. The first driving circuit and the second driving circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions of the selected word line. The first voltage signal is substantially the same as the second voltage signal. A method is also disclosed herein.Type: ApplicationFiled: March 22, 2021Publication date: August 11, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: He-Zhou WAN, Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG
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Publication number: 20220189971Abstract: A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell.Type: ApplicationFiled: April 8, 2021Publication date: June 16, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li YANG, He-Zhou WAN, Yan-Bo SONG