Patents by Inventor Yan-Cheng Lin
Yan-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967563Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.Type: GrantFiled: August 16, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
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Publication number: 20220406905Abstract: A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of AlzGa1-zN; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of AlxGa1-xN; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of AlyGa1-yN, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.Type: ApplicationFiled: May 30, 2022Publication date: December 22, 2022Inventors: Chieh-Chih HUANG, Yan-Cheng LIN, Cheng-Kuo LIN, Wei-Chou WANG, Che-Kai LIN
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Patent number: 11264379Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.Type: GrantFiled: August 18, 2020Date of Patent: March 1, 2022Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
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Publication number: 20210395457Abstract: The present invention provides a polyimide-based copolymer and electronic component and field effect transistor comprising the same. The polyimide-based copolymer comprises a copolymer of dianhydride and heterocyclic diamine, wherein the heterocyclic diamine has two benzene rings, and there are two ether bonds, two thioether bonds, or one ether bond and one thioether bond between the two benzene rings. The novel polyimide-based copolymer of the invention has excellent thermal-mechanical stability, has potential application prospects, and can be used as a substrate for flexible electronics.Type: ApplicationFiled: June 11, 2021Publication date: December 23, 2021Inventors: WEN-CHANG CHEN, MITSURU UEDA, CHUN-KAI CHEN, YAN-CHENG LIN
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Patent number: 11177379Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.Type: GrantFiled: June 19, 2019Date of Patent: November 16, 2021Assignee: WIN SEMICONDUCTORS CORP.Inventors: Chia-Ming Chang, Jung-Tao Chung, Chang-Hwang Hua, Ju-Hsien Lin, Yan-Cheng Lin, Yu-Chi Wang
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Patent number: 11081485Abstract: A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 ? above or below one of the stacked region contact interfaces of the Schottky layer.Type: GrantFiled: October 23, 2019Date of Patent: August 3, 2021Assignee: Win Semiconductors Corp.Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
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Publication number: 20210125985Abstract: A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 ? above or below one of the stacked region contact interfaces of the Schottky layer.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
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Publication number: 20200403091Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Chang-Hwang HUA, Ju-Hsien LIN, Yan-Cheng LIN, Yu-Chi WANG
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Publication number: 20200381425Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
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Patent number: 10811407Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.Type: GrantFiled: February 4, 2019Date of Patent: October 20, 2020Assignee: WIN SEMICONDUCTOR CORP.Inventors: Chia-Ming Chang, Jung-Tao Chung, Yan-Cheng Lin, Lung-Yi Tseng
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Publication number: 20200251469Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.Type: ApplicationFiled: February 4, 2019Publication date: August 6, 2020Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
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Patent number: 10643993Abstract: A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.Type: GrantFiled: March 4, 2019Date of Patent: May 5, 2020Assignee: Win Semiconductors Corp.Inventors: Hsi-Tsung Lin, Yan-Cheng Lin, Sheng-Hsien Liu
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Publication number: 20200013774Abstract: A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.Type: ApplicationFiled: March 4, 2019Publication date: January 9, 2020Inventors: Hsi-Tsung LIN, Yan-Cheng LIN, Sheng-Hsien LIU
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Patent number: 10122361Abstract: An electronic device includes a transmission interface, a driving circuit, a receiving circuit, a sampling circuit, a detecting circuit, a timing control circuit and a processing circuit. The transmission interface is for connecting to another electronic device via a connecting cable. The driving circuit outputs a backward signal via the transmission interface to the another electronic device. The receiving circuit receives a received signal including the backward signal and a forward signal from the transmission interface. The sampling circuit samples the received signal to obtain a plurality of sample results. The detecting circuit detects transitions of the sample results to obtain a plurality of detection results. The processing circuit generates a control signal according to the detection results, and adjusts a time point at which the driving circuit outputs the backward signal through the timing control circuit.Type: GrantFiled: December 5, 2016Date of Patent: November 6, 2018Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Wei-Ling Chen, Chun Wen Yeh, Yan-Cheng Lin
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Publication number: 20170324412Abstract: An electronic device includes a transmission interface, a driving circuit, a receiving circuit, a sampling circuit, a detecting circuit, a timing control circuit and a processing circuit. The transmission interface is for connecting to another electronic device via a connecting cable. The driving circuit outputs a backward signal via the transmission interface to the another electronic device. The receiving circuit receives a received signal including the backward signal and a forward signal from the transmission interface. The sampling circuit samples the received signal to obtain a plurality of sample results. The detecting circuit detects transitions of the sample results to obtain a plurality of detection results. The processing circuit generates a control signal according to the detection results, and adjusts a time point at which the driving circuit outputs the backward signal through the timing control circuit.Type: ApplicationFiled: December 5, 2016Publication date: November 9, 2017Inventors: Wei-Ling Chen, Chun Wen Yeh, Yan-Cheng Lin